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NXP Semiconductors
Bit
Symbol
11
TX_RFON_IRQ_CLR_STATU
S
10
TX_RFOFF_IRQ_CLR_STATU
S
9
RFON_DET_IRQ_CLR_STAT
US
8
RFOFF_DET_IRQ_CLR_STAT
US
7:6
RESERVED
STATE_CHANGE_IRQ_CLR_
5
STATUS
4
CARD_ACTIVATED_IRQ_CLR
_STATUS
3
MODE_DETECTED_IRQ_CL
R_STATUS
2
IDLE_IRQ_CLR_STATUS
1
TX_IRQ_CLR_STATUS
0
RX_IRQ_CLR_STATUS
[1]
Bit-field are either set by HAL or use default value from CLIF EEPROM default settings
Table 242. CLIF_INT_SET_STATUS_REG register (address 3FECh)
* = reset value
Bit
Symbol
31:30
RESERVED
29
AGC_RFOFF_DET_
IRQ_SET_STATUS
28
TX_DATA_REQ_IRQ_SET_S
TATUS
27
RX_DATA_AV_IRQ_SET_ST
ATUS
RX_BUFFER_OVERFLOW_I
26
RQ_SET_STATUS
25
TX_WATERLEVEL_IRQ_SET
_STATUS
24
RX_WATERLEVEL_IRQ_SET
_STATUS
23
RESERVED
22
RX_SC_DET_IRQ_SET_STA
TUS
21
RX_SOF_DET_IRQ_SET_ST
ATUS
UM10858
User manual
COMPANY PUBLIC
Access
Value
Description
R
0*, 1
Writing 1 to this register does clear the corresponding IRQ
STATUS flag
R
0*, 1
Writing 1 to this register does clear the corresponding IRQ
STATUS flag
R
0*, 1
Writing 1 to this register does clear the corresponding IRQ
STATUS flag
R
0*, 1
Writing 1 to this register does clear the corresponding IRQ
STATUS flag
R
0
Reserved
Writing 1 to this register does clear the corresponding IRQ
R
0*, 1
STATUS flag
R
0*, 1
Writing 1 to this register does clear the corresponding IRQ
STATUS flag
R
0*, 1
Writing 1 to this register does clear the corresponding IRQ
STATUS flag
R
0*, 1
Writing 1 to this register does clear the corresponding IRQ
STATUS flag
R
0*, 1
Writing 1 to this register does clear the corresponding IRQ
STATUS flag
R
0*, 1
Writing 1 to this register does clear the corresponding IRQ
STATUS flag
Access
Value
Description
R
0
Reserved
R
0, 1
Writing 1 to this register does set the corresponding IRQ
STATUS flag
R
0*, 1
Writing 1 to this register does set the corresponding IRQ
STATUS flag
R
0*, 1
Writing 1 to this register does set the corresponding IRQ
STATUS flag
Writing 1 to this register does set the corresponding IRQ
R
0*, 1
STATUS flag
R
0*, 1
Writing 1 to this register does set the corresponding IRQ
STATUS flag
R
0*, 1
Writing 1 to this register does set the corresponding IRQ
STATUS flag
R
0
reserved
R
0*, 1
Writing 1 to this register does set the corresponding IRQ
STATUS flag
R
0*, 1
Writing 1 to this register does set the corresponding IRQ
STATUS flag
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
UM10858
PN7462 family HW user manual
© NXP B.V. 2018. All rights reserved.
194 of 345
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