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NXP Semiconductors
HOSTIF_BUFFER_TX_CFG_REG
This register is used to configure the TX buffer
Table 336. HOSTIF_BUFFER_TX_CFG_REG (address offset 0x0048)
Bit
31:17
16
15:14
13:0
[1]
[2]
HOSTIF_BUFFER_RX0_LEN_REG
This register is used to indicate the number of bytes stored in RX buffer 0
HOSTIF_BUFFER_RX0_LEN_REG (address offset 0x004C)
Bit
31:13
12
11
10:0
UM10858
User manual
COMPANY PUBLIC
[6]
Only values 0,1 or 2 are permitted
Symbol
RESERVED
TX_EMPTY_PAYLOA
[1]
D_ENABLE
TX_HEADER_OFFSE
[1][2]
T
[1]
TX_START_ADDR
Any change to this register, is only taken into account if the buffer is not in use (TX_BUFFER_LOCK = 0).
However, the register itself is updated.
Only values 0,1 or 2 are permitted
Symbol
RESERVED
RX0_PEC_OK
RX0_PEC_RECEIVED R
RX0_LENGTH
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
Access
Reset
Description
Value
R
0
Reserved
R/W
0
1 - send empty payload packets (header
and CRC only).
Not applicable to Native Mode.
R/W
0x02
Number of bytes to skip in first word of
buffer before sending to Host.
Not applicable to Native Mode.
R/W
0
Word start address of TX buffer. Bits [1:0]
are unused.
Access
Reset
Description
Value
R
0
Reserved
R
0
1 - Last byte received matched computed
PEC. Only valid if RX0_PEC_RECEIVED
is 1
0
1 - Last received was a PEC. 0- hardware
could not detected if last received byte
was a PEC, payload analysis required.
R
0
Number of bytes received in buffer RX0
(active when
HOSTIF_CONTROL_REG.NCI_LENGTH_M
ODE=1)
314514
UM10858
PN7462 family HW user manual
© NXP B.V. 2018. All rights reserved.
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