Register Description - NXP Semiconductors PN7462 series User Manual

NXP Semiconductors
Name
PCR_INT_ENABLE_REG
PCR_INT_CLR_STATUS_RE
G
PCR_INT_SET_STATUS_RE
G

8.8 Register description

Table 72. PCR_GPREG0_REG (address offset 0x00)
Bit Symbol
31:0 PCR_GPREG0
Table 73. PCR_GPREG1_REG (address offset 0x04)
Bit Symbol
31:0 PCR_GPREG1
Table 74. PCR_GPREG2_REG (address offset 0x08)
Bit Symbol
31:0 PCR_GPREG2
Table 75. PCR_SYS_REG (address offset 0x0C)
Bit Symbol
31:12 RESERVED
11
AUTOMATIC_CT_DEACT
10
AUTOMATIC_HPD
9
PVDD_INT
8
ENABLE_CT
7
PVDD_M_IRQ_VAL
6 PVDD_M_IRQ_EN
UM10858
User manual
COMPANY PUBLIC
Address Width Access
(bits)
Offset
0x3FE4 32 r-m
0x3FE8 32 -wm
0x3FEC 32 -wm
Access Value
R/W 0
Access Value
R/W 0
Access Value
R/W 0
Access Value
rw 0x00
rw 0x00
rw 0x00
rw 0x00
rw 0x01
rw 0x00
rw 0x00
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
PN7462 family HW user manual
Reset value Description
0x00000000 interrupt enable
0x00000000 interrupt clear status
0x00000000 interrupt set status
Description
general-purpose register 0 for SW
Description
general-purpose register 1 for SW
Description
general-purpose register 2 for SW
Description
Reserved
1: Enables automatic initiation of CT deactivation
sequence when VBUSP voltage goes below
programmed range.
1: Enables PCR to go automatically into HPD state when
the VBUS voltage goes below programmed voltage of
2.3 V/2.7 V
0: PCR stays in operating state even if VBUS goes
below threshold voltage
Indicates that PVDD is being supplied using internal
PVDD LDO
1: Enable Internal PVDD LDO
1: Enable the Contact interface.
0: Disable Contact Interface
Selects the PVDD_M voltage trigger level
0: PVDD_M voltage trigger level 1.8 V
1: PVDD_M voltage trigger level 3.3 V
Enables the PVDD_M IRQ
UM10858
© NXP B.V. 2018. All rights reserved.
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