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NXP Semiconductors
TOC Value
75h
77h
7Ch
F3h
F7h
UM10858
User manual
COMPANY PUBLIC
Operating Mode
count will not be affected and the new count value will be taken into account at the next start bit.
An interrupt is given, and bit TO2 is set within register ct_usr2_reg when the terminal count is
reached. Counting the value stored in register ct_tor3_reg is started after 73h is written in
register ct_toc_reg. An interrupt is given, and bit TO3 is set within register ct_usr2_reg when the
terminal count is reached. The counter sHALl be stopped before reloading new value in
ct_tor3_reg register. The counters are stopped by writing 00h in register ct_toc_reg. In this
configuration, registers ct_tor3_reg and ct_tor2_reg must not be all zero.
Counter 1 is an 8-bit auto-reload counter, and counters 3 and 2 form a 16-bit counter. Counter 1
starts counting the content of register ct_tor1_reg on the first start bit (reception or transmission)
detected on pin I/O after 75h is written in register ct_toc_reg. When counter 1 reaches its
terminal count, an interrupt is given, bit TO1 in register ct_usr2_reg is set, and the counter
automatically restarts the same count until it is stopped. Changing the content of register
ct_tor1_reg during a count is not allowed. Counting the value stored in registers ct_tor3_reg and
ct_tor2_reg is started on the first start bit detected on pin I/O (reception or transmission) after
the value has been written, and then on each subsequent start bit. It is possible to change the
content of registers ct_tor3_reg and ct_tor2_reg during a count; the current count will not be
affected and the new count value will be taken into account at the next start bit. An interrupt is
given, and bit TO3 is set within register ct_usr2_reg when the terminal count is reached. The
counters are stopped by writing 00h in ct_toc_reg register. In this configuration, registers
ct_tor3_reg, ct_tor2_reg and ct_tor1_reg must not be all zero.
Counters 1, 2 and 3 are three independent 8-bit counters. Counter 1 is an 8-bit auto-reload
counter which starts counting the content of register ct_tor1_reg on the first start bit (reception
or transmission) detected on pin I/O after 77h is written in register ct_toc_reg. When counter 1
reaches its terminal count, an interrupt is given, bit TO1 in register ct_usr2_reg is set, and the
counter automatically restarts the same count until it is stopped. Changing the content of
register ct_tor1_reg during a count is not allowed. Counter 2 starts counting the content of
register ct_tor2_reg on the first start bit (reception or transmission) detected on pin I/O after 77h
is written in register ct_toc_reg, and then on each subsequent start bit. It is possible to change
the content of register ct_tor2_reg during a count; the current count will not be affected and the
new count value will be taken into account at the next start bit. An interrupt is given, and bit TO2
is set within register ct_usr2_reg when the terminal count is reached. Counting the value stored
in register ct_tor3_reg is started after 77h is written in register ct_toc_reg. An interrupt is given,
and bit TO3 is set within register ct_usr2_reg when the terminal count is reached. The counter
sHALl be stopped before reloading new value in ct_tor3_reg register. The counters are stopped
by writing 00h in register ct_toc_reg. In this configuration, registers ct_tor3_reg, ct_tor2_reg and
ct_tor1_reg must not be all zero.
Counters 3, 2 and 1 are wired as a single 24-bit counter. Counting the value stored in registers
ct_tor3_reg, ct_tor2_reg and ct_tor1_reg is started on the first start bit detected on pin I/O
(reception or transmission) after the value has been written, and then on each subsequent start
bit. It is possible to change the content of registers ct_tor3_reg, ct_tor2_reg and ct_tor1_reg
during a count; the current count will not be affected and the new count value will be taken into
account at the next start bit. An interrupt is given, and bit TO3 is set within register ct_usr2_reg
when the terminal count is reached. The counter is stopped by writing 00H in register
ct_toc_reg. In this configuration, registers ct_tor3_reg, ct_tor2_reg and ct_tor1_reg must not be
all zero.
Same configuration as value 73h, except that the 8-bit counters will be stopped at the end of the
12th ETU following the first start bit detected after F3h has been written in ct_toc_reg register.
Same configuration as value 77h, except that the 8-bit counters will be stopped at the end of the
12th ETU following the first start bit detected after F7h has been written in ct_toc_reg register.
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
UM10858
PN7462 family HW user manual
© NXP B.V. 2018. All rights reserved.
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