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NXP Semiconductors
Bit
Symbol
5
TX_UNDERSHOOT_
PROT_LAST_SC_E
NABLE
4:1
TX_UNDERSHOOT_
PATTERN_LEN
0
TX_UNDERSHOOT_
PROT_ENABLE
Table 205. CLIF_RX_CONFIG_REG register (address 005Ch)
* = reset value
Bit
Symbol
31
RX_PARITY_EMD_
ON_SO VER
30
RX_MISSING_PARI
TY_IS_EMD
29
RX_ADVANCED_EM
D_ENABLE
28
RX_PARITY_ERRO
R_IS_EMD
27:25
RX_EMD_SUP
24
RX_COLL_IS_DATA
_ERROR
23
VALUES_AFTER_C
OLLISION
22
RX_CRC_ALLOW_B
ITS
21
RX_FORCE_CRC_
WRITE
20
RESERVED
UM10858
User manual
COMPANY PUBLIC
Access
Value
R/W
0* - 1
R/"
0* - Fh
R/W
0*, 1
Access
Value
R/W
0*,1
R/W
0*,1
R/W
0*,1
R/W
0*, 1
R/W
0*- 7h
000
001
010
011
100
101 - 111
R/W
0*, 1
R/W
0*, 1
0
1
R/W
0*, 1
R/W
0*, 1
R
0
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
PN7462 family HW user manual
Description
This mode activates the undershoot prevention circuit only
for the last sub-carrier cycle for card-mode transmission.
Note: The bit TX_UNDERSHOOT_PROT_ENABLE must not
be set for this mode.
Defines length of the undershoot prevention pattern (value
+1). The pattern is applied starting from the MSB of the
defined pattern, all other bits are ignored.
If set to 1, the undershoot protection is enabled.
Description
If set, decision if EMD due to parity error is taken at saver
If set, a missing parity bit in the 4th byte is treated as - EMD
(for EMD option 3/4
If set, new EMD options for PN7462 family are enabled
If set to 1 a parity error in the 3rd/4th byte (depending on
RX_EMD_SUP setting) is interpreted as an EMD error.
Otherwise it is interpreted as a parity error.
Defines EMD suppression mechanism
Off
EMD suppression according to ISO14443
EMD suppression according to NFC Forum (with respect to
the first 3 characters)
EMD suppression according to NFC Forum (with respect to
the first 4characters)
EMD suppression according to NFC Forum (with respect to
the first 4characters, all valid frames <4 bytes are ignored)
reserved
If set to 1, a collision is treated as a data integrity error
(especially for ISO14443-4)
This bit defined the value of bits received after a collision
occurred.
All received bits after a collision will be cleared.
All received bits after a collision keep their value.
Set to 1, a frame with less than one byte length is written to
ram, when the CRC is enabled otherwise it is discarded.
Set to 1, the received CRC byte(s) are written to ram. In
normal operation (if this bit is set to 0) CRC bytes are only
checked and removed from the data stream.
Reserved
UM10858
© NXP B.V. 2018. All rights reserved.
166 of 345
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