NXP Semiconductors PN7462 series User Manual page 198

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NXP Semiconductors
DPC_TIME
DPC_XI
AGC_CONTROL
DPC_THRSH_HI
GH
DPC_THRSH_L
OW
DPC_DEBUG
DPC_AGC_SHIF
T_VALUE
DPC_AGC_GEA
R_LUT_SIZE
DPC_AGC_GEA
R_LUT
UM10858
User manual
COMPANY PUBLIC
0x201328
wControlCycle
0x201353
bAgcXi
0x20132A
wAgcFastModeConfig
0x201334
wAgcTrshHigh
0x20132C
wAgcTrshLow
0x201354
bDebug
0x201355
bAgcShiftValue
0x201356
bSizeOfLUT
0x201357
bConfigLUT
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
UM10858
PN7462 family HW user manual
R/W
2
Sets the value for
the periodic
regulation. Time
base is
1/20 MHz.
(Example: Value of
20000 is equal to 1
ms)
R/W
1
Trim Value of the
AGC value
R/W
2
Controls the AGC
loop
bit15..14 RFU
bit13 StepSize
Enable
bit12..11 StepSize
bit10... Duration
Enable
bit9..0 Duration
R/W
30
Defines the AGC
high threshold for
each gear.
Number of gears
can be 1..15
R/W
2
Defines the AGC
low threshold for
initial gear.
R/W
1
Enables the debug
signals
R/W
1
Shift Value for the
AGC dynamic low
adoption to
prevent oscillation
R/W
1
Defines the number
of gears for the
lookup table (LUT,
value can be
between 1...15)
R/W
15
Defines the Gear
Setting for each
step size starting
with Gear0 up to 15
gears. Each entry
contains a
definition for the
DPC_CONFIG
register content.
Bits
© NXP B.V. 2018. All rights reserved.
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