NXP Semiconductors PN7462 series User Manual page 246

NXP Semiconductors
Bit Symbol
2 SET_ENABLE_NACK
1 SET_ENABLE_ARB_FAIL
URE
0 SET_ENABLE_TRN_COM
PLETED
14.1.9.14 INT_STATUS_REG
This register is a collection of Interrupt Status commands. Writing 1 to this register does
set the corresponding Interrupt Request ENABLE flag. Writing 0 to this register has no
effect.
Table 289. INT_STATUS_REG (address offset 0x3FE0)
Legend: * reset value; <= mandatory value
Bit Symbol
31:12 RESERVED
11 TX_FIFO_THRES
10 RX_FIFO_THRES
9 FIFO_EMPTY
8 FIFO_FULL
7:4 RESERVED
3 I2C_BUS_ERROR
2 NACK
1 ARB_FAILURE
0 TRN_COMPLETED
14.1.9.15 INT_ENABLE_REG
This register is a collection of Interrupt Enable commands. Writing 1 to this register does
set the corresponding Interrupt Request ENABLE flag. Writing 0 to this register has no
effect.
Table 290. INT_ENABLE_REG (address offset 0x3FE4)
Legend: * reset value; <= mandatory value
Bit Symbol
31:12 RESERVED
11 ENABLE_TX_FIFO_THRE
S
10 ENABLE_RX_FIFO_THRE
S
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Access Value Description
W 0x0* Writing 1 to this register does set the corresponding IRQ
ENABLE flag
W 0x0* Writing 1 to this register does set the corresponding IRQ
ENABLE flag
W 0x0* Writing 1 to this register does set the corresponding IRQ
ENABLE flag
Access Value Description
R 0x0* reserved
R 0x0* Indicates that the FIFO threshol d is reached whil e I2C
transmission is on-going
Indicates that the FIFO threshol d is reached whil e I2C reception
R 0x0*
is on-going
R 0x0* Indicates that the FIFO empty condition is reached while I2C
transmission is on-going
R 0x0* Indicates that the FIFO full condition is reached while I2C
reception is on-going
R 0x0* reserved
R 0x0* Indicates an I2C bus error occurred
R 0x0* Indicates an I2C slave didn't acknowledge the I2C master
request
R 0x0* Indicates an I2C master arbitration failure
R 0x0* Indicates an I2C master completed the I2C transmission or I2C
reception
Access Value Description
R 0x0* reserved
R 0x0* If this bit is 1 the corresponding IRQ can propagate to the
CPUs IRQ controller
R 0x0* If this bit is 1 the corresponding IRQ can propagate to the
CPUs IRQ controller
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Rev. 1.4 — 14 May 2018
314514
UM10858
PN7462 family HW user manual
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