NXP Semiconductors PN7462 series User Manual page 158

NXP Semiconductors
Bit Symbol
3 RX_ACTIVE
2:0 TRANSCEIVE_STATE
Table 189. CLIF_TRANSCEIVE_CONTROL_REG register (address 000Ch)
* = reset value
Bit Symbol
31:30 RESERVED
[1]
29:24 INTERNAL_USE
23:18 RESERVED
[1]
17 INTERNAL_USE
[1]
16 INTERNAL_USE
15:8 TX_BITPHASE
7 RESERVED
[1]
6 INTERNAL_USE
[1]
5 INTERNAL_USE
[1]
4 INTERNAL_USE
[1]
3 INTERNAL_USE
2 RX_MULTIPLE_ENABLE
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User manual
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Access Value Description
R 0*, 1 This bit indicates activity of the RXDecoder. If 1 a data reception
is ongoing, otherwise the RXDecoder is in idle state.
R 0* - 5 These registers hold the command bits
0* IDLE state
1 WaitTransmit state
2 Transmitting state
3 WaitReceive state
4 WaitForData state
5 Receiving state
6 WaitLoopBack state
7 LoopBack state
Access Value Description
R 0 reserved
R/W 0* - for internal use
111111b
xxxxx1 IDLE state enabled to trigger IRQ
xxxx1x WaitTransmit state enabled to trigger IRQ
xxx1xx Transmitting state enabled to trigger IRQ
xx1xxx WaitReceive state enabled to trigger IRQ
x1xxxx WaitForData state enabled to trigger IRQ
1xxxxx Receiving state enabled to trigger IRQ
R 0 Reserved
R/W 0*, 1 for internal use
R/W 0*, 1 for internal use
R/W 0* - FFh Defines the number of 13.56 MHz cycles used for
adjustment of TX_wait to meet the FDT.
R 0 reserved
R/W 0*, 1 for internal use
D 0*, 1 for internal use
R/W 0*, 1 for internal use
R/W 0*, 1 for internal use
R/W 0*, 1 If this bit is set to 1, the receiver is re-activated after the end
of a reception. A status byte is written to the RAM containing
all relevant status information of the frame.
Note: Data in RAM is word aligned therefore empty bytes of
a data Word in RAM are padded with 0x00 bytes. SW has to
calculate the correct address for the following frame.
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
UM10858
PN7462 family HW user manual
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