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• Transmission:
PEC=0: no action, the transmission doesn't stop.
PEC>0 (automatic mode): the transmission stops. The software will deactivate the card:
the parity error counter will be reset by hardware when activating. If necessary, the
firmware has the possibility to pursue the transmission. By reading the number of bytes
present into the FIFO (ffl bits), it can determine which character has been naked PEC +1
times by the card. It will then flush the FIFO (FIFO flush bit). The next step consists in
unlocking the transmission using dispe bit. By writing this bit at logic level one (and then
at logic level zero if the firmware still wants to check parity errors), the transmission is
unlocked. The firmware can now write bytes into the FIFO.
• Turnaround Reception -> Transmission:
13.5 Connect an external TDA
The PN7462 family can handle more than one smart card by controlling an extra contact
interface front-end (typically TDA product from NXP).
In this use case, the PN7462 family is the main controller for the electrical and protocol
part for the main card slot, while the secondary slots are electrically controlled by an
extra contact front-end interface (TDA), the PN7462 family being the protocol controller
for these extra slots.
When such a design is used, several smart cards can be activated at the same time, but
the communication with each smart card has to go sequentially: it is not possible to
UM10858
User manual
COMPANY PUBLIC
− When the micro-controller reads a character, the FIFO size pointer is
decremented.
− A read operation when the FIFO is empty will not cause any action for the FIFO
(size pointer unchanged). In this case, 0 is read.
− The micro-controller can write a character into the FIFO whilst the UART is in
transmission mode and if the FIFO is not full. If the FIFO contains already 32
characters, the write operation is not taken into account.
− The FIFO commands the transmission. If its size pointer is one or more, the FIFO
starts the transmission by loading the first character to transmit in the
Transmission block. Then, the Transmission block will manage the transmission
to the card. The FIFO size pointer is decremented at 9.5 ETUs.
− If a parity error interrupt occurs after one or more retransmission(s) (T=0), there
are two cases:
− There is a hardware protection when switching from reception to transmission
mode. If the micro-controller sets to logic 1 the bit T/R for example between 10.5
(ft occurs) and 11.8 ETUs (reception finished), only the FIFO switches in
transmission mode and not the rest of the UART which remains in reception
mode. This allows the micro-controller to write characters into the FIFO. At 11.8
ETUs, the whole UART switches in transmission mode.
− The FIFO is in transmission mode when the bit T/R is set to logic 1, else in
reception mode. The transmission starts when the whole UART is in transmission
mode, that is to say when the internal bit T/R in register ct_ucr1_reg is set to logic
1.
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
UM10858
PN7462 family HW user manual
© NXP B.V. 2018. All rights reserved.
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