NXP Semiconductors PN7462 series User Manual page 68

NXP Semiconductors
Table 61. CLKGEN_CLIF_PLL1_CONTROL_REG (address 0018h)
Bit Symbol
31:28 RESERVED
27 CLIF_PLL_LIMUP_OFF1
26 CLIF_PLL_FREQ_LIM1
25:24 CLIF_PLL_SELP1
23:22 CLIF_PLL_SELI1
21:20 CLIF_PLL_SELR1
19 CLIF_PLL_FUNC_TEST2_P1
18 CLIF_PLL_FUNC_TEST1_P1
17:12 CLIF_PLL_DIVP1
11 CLIF_PLL_FUNC_TEST2_M1
10 CLIF_PLL_FUNC_TEST1_M1
9:3 CLIF_PLL_DIVM1
2 CLIF_PLL_BYPASS_LOCK1
1 CLIF_PLL_FUNC_TEST2_LOCK1
0 CLIF_PLL_FUNC_TEST1_LOCK1
7.7.2 CLIF PLL CONTROL2 REG
The CLKGEN_CLIF_PLL2_CONTROL_REG register contains the CLIF PLL multiplier
and divider values. Changes to CLKGEN_CLIF_PLL2_CONTROL_REG register do not
take effect until a correct CLIF PLL feed sequence has been given. Calculations for the
USB PLL frequency, and multiplier and divider values are found
Table 62. CLKGEN_CLIF_PLL2_CONTROL_REG (address 001Ch)
Bit Symbol
31:28 RESERVED
27 CLIF_PLL_LIMUP_OFF2
26 CLIF_PLL_FREQ_LIM2
25:24 CLIF_PLL_SELP2
23:22 CLIF_PLL_SELI2
21:20 CLIF_PLL_SELR2
19 CLIF_PLL_FUNC_TEST2_P2
18 CLIF_PLL_FUNC_TEST1_P2
17:12 CLIF_PLL_DIVP2
11 CLIF_PLL_FUNC_TEST2_M2
10 CLIF_PLL_FUNC_TEST1_M2
9:3 CLIF_PLL_DIVM2
2 CLIF_PLL_BYPASS_LOCK2
UM10858
User manual
COMPANY PUBLIC
Access Value Description
R/W 0x00 Reserved
R/W 0x00 pulse limiter for CLIF_PLL 1
R/W 0x00 frequency limiter for CLIF_PLL 1
R/W 0x02 Pins to select the BW of CLIF_PLL 1
R/W 0x03 Pins to select the BW of CLIF_PLL 1
R/W 0x02 Pins to select the BW of CLIF_PLL 1
R/W 0x00 1: Enable functional CLIF_PLL chain test of divider P1
R/W 0x00 1: Enable functional divider test of divider P1
R/W 0x3B Feedback divider ratio P1
R/W 0x00 1: Enable functional CLIF_PLL test chain of divider M1
R/W 0x00 1: Enable functional divider test of divider M1
R/W 0x32 Feedback divider ratio M1
R/W 0x00 Bypass of Lock1
1: Bypass clif_pll_lock1
R/W 0x00 1: Enable functional CLIF_PLL test chain of lock detector
1
R/W 0x00 1: Enable functional divider test of lock detector 1
Access Value Description
R/W 0x00 Reserved
R/W 0x00 pulse limiter for CLIF_PLL 2
R/W 0x00 frequency limiter for CLIF_PLL 2
R/W 0x02 Pins to select the BW of CLIF_PLL 2
R/W 0x03 Pins to select the BW of CLIF_PLL 2
R/W 0x02 Pins to select the BW of CLIF_PLL 2
R/W 0x00 1: Enable functional CLIF_PLL chain test of divider P2
R/W 0x00 1: Enable functional divider test of divider P2
R/W 0x12 Feedback divider ratio P2
R/W 0x00 1: Enable functional CLIF_PLL test chain of divider M2
R/W 0x00 1: Enable functional divider test of divider M2
R/W 0x3C feedback divider ratio M2
R/W 0x00 Bypass of Lock2
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
UM10858
PN7462 family HW user manual
Section 7.2.
© NXP B.V. 2018. All rights reserved.
68 of 345