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NXP Semiconductors
Table 160. TIMERS_TIMER3_TIMEOUT_REG (address offset 0x0028)
Bit
Symbol
31:0
TIMER3_TIMEOUT
Table 161. TIMERS_TIMER3_COUNT_REG (address offset 0x002C)
Bit
Symbol
31:0
TIMER3_COUNT
Table 162. TIMERS_WDOG_CONTROL_REG (address offset 0x0030)
Bit
Symbol
31:1
RESERVED
0
WDOG_KICK
Table 163. TIMERS_WDOG_TIMEOUT_REG (address offset 0x0034)
Bit
Symbol
31:10
RESERVED
9:0
WDOG_TIMEOUT
Table 164. TIMERS_WDOG_TRIGGER_INT_REG (address offset 0x0038)
Bit
Symbol
31:10
RESERVED
9:0
WDOG_INT_THRESHOLD
Table 165. TIMERS_WDOG_COUNT_REG (address offset 0x003C)
Bit
Symbol
31:10
RESERVED
9:0
WDOG_COUNT
UM10858
User manual
COMPANY PUBLIC
Reset Value
Access Type
0
R/W
Reset Value
Access Type
0
R
Reset Value
Access Type
0
R
0
D
Reset Value
Access Type
0
R
0
R/W
Reset Value
Access Type
0
R
0
R/W
Reset Value
Access Type
0
R
0
R
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
UM10858
PN7462 family HW user manual
Description
Initial count value of Timer3 in step size of
[2]
0.30 ms
. If set to 0, this feature is disabled.
Description
Current count value of Timer3 in step size of
50 ns
Description
reserved
1: re-initialize the Watchdog Timer to value
WDOG_TIMEOUT
0: no effect
Description
reserved
Initial count value of Watchdog Timer in step
size of 21.5 ms
If set to 0, this feature is disabled.
Description
reserved
Count value of Watchdog Timer which
triggers interrupt intreq_wdog_o
Description
reserved
Current count value of Watchdog Timer in
step size of 21.5 ms
© NXP B.V. 2018. All rights reserved.
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