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6. CLK cycles with RST at logic level one, the bit MUTE is set to logic level one.
7. If the card answers within the correct time window, the CLK cycles count is stopped
The picture below shows the timings checked by the ATR counter:
Fig 37. ATR counter timings checked (with default values)
The bits EARLY and MUTE signal an interrupt when set to logic level one (see the
registers description).
The sequence mentioned above relates to a cold reset (left part of
mute (has not answered), the application may start a warm reset by setting WARM bit to
logic level one (see the registers description). Then, the ATR counter set RST to logic
level zero and performs the same timing checks (right part of
13.4.2 FIFO
The FIFO is used for both Reception and Transmission modes. This block receives
characters from the card via the Reception block and provides characters written by the
micro-controller to the Transmission block. Its depth is 32 bytes.
• Reception:
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and the application may send commands to the card.
− In reception mode, when a received character is correct (no parity error) at 10.5
ETUs (T=0), it is loaded into the FIFO which size pointer is incremented.
− If the FIFO size pointer equals 32, no more character can be loaded into the
FIFO. An Overrun interrupt will be generated by the ct_usr1_reg register to mean
that at least one character will be lost.
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
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UM10858
PN7462 family HW user manual
Fig
37). If the card is
Fig
37).
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