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NXP Semiconductors
Name
EE_INT_CLR_STATUS
EE_INT_SET_STATUS
3.7 Register description
Table 7.
EE_CTRL (address offset 0x0000h)
Bit
Symbol
31:16
RESERVED
15
ECC_PF_AHB_ERROR_ENABLE
14
PFLASH_READ_PREFETCH_DI
S
13
BLOCK_1_COD
12
BNWSENS_1_COD
11
SKIPPRG_1_COD
10
STOP_1_COD
9
PFLASH_DOUT_SYNCHRO_DI
S
8
POWER_DOWN_1_COD
7
BLOCK_0_COD
6
BNWSENS_0_COD
5
SKIPPRG_0_COD
4
STOP_0_COD
3
FAST_COD
2
POWER_DOWN_0_COD
1
FAST_DAT
0
power_down_dat
Table 8.
EE_DYN (address offset 0x0004h)
Bit
Symbol
31:24
RESERVED
UM10858
User manual
COMPANY PUBLIC
Address
Width
Access
offset
(bits)
0FE8h
32
W
0FECh
32
W
Access Value
-
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Value
-
0
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
PN7462 family HW user manual
Reset value
Description
0000_0000h
Interrupt CLR_STATUS
commands
0000_0000h
Interrupt SET_STATUS
commands
Description
Reserved
when '1' enables the AHB error
generation when FLASH read data cannot
be corrected by the ECC mechanism and
automatically set the FAST_COD bit to '0'
to put the FLASH in slow mode.
When '1' disables read prefetching for the
Flash memories
Block mode for FLASH_1
voltage drop sensor enable for FLASH_1
skip program if erase fails for FLASH_1
stop ramp-up at low power for FLASH_1
when '0' output PAGEFLASH data is
synchronized with the system clock to
ensure that following ECC calculation is
made on stable data. It is automatically
set to '1' if FAST_COD = '1'.
power down FLASH_1 block
block mode for FLASH_0
voltage drop sensor enable for FLASH_0
skip program if erase fails for FLASH_0
stop ramp-up at low power for FLASH_0
fast access for both FLASH_0 and
FLASH_1. It is automatically set to '0' if
EE_CTRL.ECC_PF_AHB_ERROR_ENAB
LE register is set to '1'
power down FLASH block
fast EEPROM data access
power down EEPROM block
Description
Reserved
UM10858
© NXP B.V. 2018. All rights reserved.
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