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NXP Semiconductors
14.1.2 General description
A typical I ²C bus configuration is shown in
serial clock pulses and the START and STOP conditions. Depending on the state of the
direction bit (R/W), two types of data transfers are possible on the I2C-bus:
• Data transfer from a master transmitter to a slave receiver. The first byte transmitted
• Data transfer from a slave transmitter to a master receiver. The first byte (the slave
A transfer is ended with a STOP condition or with a Repeated START condition. Since a
Repeated START condition is also the beginning of the next serial transfer, the I2C bus
will not be released.
Fig 42. I2C bus configuration
The I2C Master can operate in two modes: I2C Master Transmitter and I2C Master
Receiver.
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by the master is the slave address. Next follows a number of data bytes. The slave
returns an acknowledge bit after each received byte.
address) is transmitted by the master. The slave then returns an acknowledge bit.
Next follows the data bytes transmitted by the slave to the master. The master
returns an acknowledge bit after all received bytes other than the last byte. At the
end of the last received byte, a "not acknowledge" is returned.
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
Fig
42. The master device generates all of the
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