NXP Semiconductors PN7462 series User Manual page 102

NXP Semiconductors
Bit Symbol
3:2
SCL_PUPD
1 SDA_SLEW
0 SCL_SLEW
Table 111. PCR_ANA_TX_STANDBY_REG (address offset 0xA8)
Bit Symbol
31:5 RESERVED
4 TX_GSN_SRC_SEL
3:0 TX_GSN_CW_SB
Table 112. PCR_ANA_TXPROT_REG (address offset 0xAC)
Bit Symbol
31:5 RESERVED
4
RX_PROT_IDDQ
3 TXPROT_ENABLE_AUTO_
FREEZE
2 TXPROT_LIM_FREEZE
1 TXPROT_PD_VREF
0
TXPROT_ENABLE
Table 113. PCR_SPIM_REG (address offset 0xB4)
Bit Symbol
31:20 RESERVED
19
SPIM_NSS1_EN
18
SPIM_MOSI_EN_OUT
17
SPIM_MISO_EN_OUT
UM10858
User manual
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Access Value Description
11: Enable pull down
Enables pull up/down functionality on SCL
10: Enable pull up
rw 0x00 11: Enable pull down
rw 0x00 1: Enables SDA slew rate
rw 0x00 1: Enables SCL slew rate
Access Value Description
rw 0x00 Reserved
rw 0x00 Source of GSN value (0... PCR, 1... CLIF)
rw 0x00 GSN Value for standby mode
Access Value Description
rw 0x00 Reserved
1: Set RX protection to power down for Iddq
rw 0x00 measurement
Enable automatic freeze during typeB demodulation:
rw 0x00 typeB_det =1 -> freeze; else -> no freeze
rw 0x00 Freeze limiter impedance, active high
rw p Power down reference voltage generation for tx-prot
1: Enables tx protection
rw 0x01 0: Disables tx protection
Access Value Description
rw 0x00 Reserved
SPIM master second slave enabled: slave 1, slave 0
enabled by default.
1: slave 1 enabled
rw 0x00 0: slave 0 enabled
SW control for SPIM_MOSI ECS when
SPIM_SW_ENABLE='1'
rw 0x00 1: SPIM MOSI enabled as output
SW control for SPIM_MISO ECS when
SPIM_SW_ENABLE='1'
rw 0x00 1: SPIM MISO enabled as output
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
UM10858
PN7462 family HW user manual
© NXP B.V. 2018. All rights reserved.
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