NXP Semiconductors PN7462 series User Manual page 307

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NXP Semiconductors
Bit
21
20:17
16
15
14:11
10:7
6
5
4
UM10858
User manual
COMPANY PUBLIC
Symbol
Access
WATERLEVEL_REAC
W
HED_SET_ENABLE
RX_BUFFER_OVERF
W
LOW_SET_ENABLE
CRC_NOK_SET_ENAB
W
LE
TX_TIMEOUT_SET_E
W
NABLE
RX_FRAME_OVERFL
W
OW_SET_ENABLE
RX_FRAME_UNDERF
W
LOW_SET_ENABLE
TX_FRAME_NOT_AVAI
W
LABLE_SET_ENABLE
RX_BUFFER_NOT_A
W
VAILABLE_SET_ENA
BLE
EOT_SET_ENABLE
W
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
PN7462 family HW user manual
Reset
Description
Value
0
1 - set enable for water level reached
interrupt
0 - no effect
0
0001 - set enable for max buffer size
interrupt for RX buffer 0
0010 - set enable for max buffer size
interrupt for RX buffer 1
0100 - set enable for max buffer size
interrupt for RX buffer 2
1000 - set enable for max buffer size
interrupt for RX buffer 3
0000 - no effect
0
1 - set enable for data-link Layer CRC
error interrupt
0 - no effect
0
1 - set enable for inter-character timeout
(TIC) exceeded on transmitted frame
interrupt
0 - no effect
0
0001 - set enable for frame overflow
interrupt for RX buffer 0
0010 - set enable for frame overflow
interrupt for RX buffer 1
0100 - set enable for frame overflow
interrupt for RX buffer 2
1000 - set enable for frame overflow
interrupt for RX buffer 3
0000 - no effect
0
0001 - set enable for frame underflow
interrupt for RX buffer 0
0010 - set enable for frame underflow
interrupt for RX buffer 1
0100 - set enable for frame underflow
interrupt for RX buffer 2
1000 - set enable for frame underflow
interrupt for RX buffer 3
0000 - no effect
0
1 - set enable for TX frame not available
interrupt
0 - no effect
0
1 - set enable for no receive buffers
available interrupt
0 - no effect
0
1 - set enable for EOT interrupt
0 - no effect
UM10858
© NXP B.V. 2018. All rights reserved.
307 of 345

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