Boot Reason Decoding - NXP Semiconductors PN7462 series User Manual

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These reset sources trigger the reset generator that generates a global reset pulse. The
Reset Generator is active high-level sensitive to the reset sources. As long as one reset
source is high, the global reset will be active. After releasing the reset source, the reset
pulse will be prolonged to at least one cycle. The power-on reset sequence is asserted
when the device is powered up. It is used to keep the system in reset state until proper
supply conditions are established. This point is achieved when the internal supply voltage
reaches 1.55 V.
When the internal reset is removed, the processor begins executing at address 0, which
is initially the reset vector mapped from the boot block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.

8.2 Boot reason decoding

Table 67. Boot reason decoding
PCR_STATUS.boot_reason Values
startup_por
Rfld
wuc_cnt
int_aux
Ct
i2c
RESERVED
Spi
usb_resume
soft_reset
Wdog
Tvddmon
hif_reset
temp0
temp1
no_pvdd
pvdd_ilim
gpio
hsu
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reflected in
register
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
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Rev. 1.4 — 14 May 2018
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PN7462 family HW user manual
Description
Analog Reset Sources (Startup Por or leave
from HPD or VEN)
RF Level Detector wakeup
Wakeup Timer
Contact uart int_aux pad gives an interrupt
Contact card presence is detected
I2C address detected
Reserved
SPI slave received transaction
USB Resume signaling from Host
Soft reset given by software
Watch dog timer timeout or ARM reset
5V detected by TVDD monitor
VEN from low to high back (only for test
purpose) Ii2c slave or smb slave requested for
reset
Neg-edge detected for Temperature error from
temperature sensor 0
Neg-edge detected for Temperature error from
temperature sensor 1
PVDD dropped
Pvdd current limiter input has become 01
Gpio interrupt
HSUART transaction detected
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