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NXP Semiconductors
Bit
7
6
5
4
3
2
1
0
[1]
• BAUDRATE
• SLAVE_SELECT
• MSB_FIRST
• CPHA
• CPOL
• NSS_PULSE
• NSS_POLARITY
UM10858
User manual
COMPANY PUBLIC
Symbol
[1]
MSB_FIRST
CPHA [1]
CPOL [1]
NSS_VAL
NSS_CTRL
RESERVED
[1]
NSS_PULSE
[1]
NSS_POLARITY
The following Register bit fields are not updated during an on-going SPI communication.
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
Access
Reset
Description
Value
R/W
0
If set, MS bit of a byte is transmitted &
received first.
If cleared, LS bit of a byte is transmitted &
received first.
R/W
0
This bit is used to select the SPI clock
format. A change of this bit will abort a
transmission in progress and force the SPI
system into idle state.
1 = Sampling of data occurs at even edges
(2,4,6,...,16) of the SCK clock
0 = Sampling of data occurs at odd edges
(1,3,5,...,15) of the SCK clock
R/W
0
This bit selects an inverted or non-inverted
SPI clock. To transmit data between SPI
modules, the SPI modules must have
identical CPOL values. A change of this bit
will abort a transmission in progress and
force the SPI system into idle state.
1 = Active-low clocks selected. In idle state
SCK is high.
0 = Active-high clocks selected. In idle state
SCK is low.
R/W
0
Value to output to nss for the selected slave
if NSS_CTRL=1
R/W
0
1: Override NSS value with NSS_VAL
R
0
Reserved
R/W
1
1: a pulse on NSS is generated between 2
bytes
R/W
0
0: NSS active low
314514
UM10858
PN7462 family HW user manual
© NXP B.V. 2018. All rights reserved.
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