NXP Semiconductors PN7462 series User Manual page 216

NXP Semiconductors
13.6.2.2 Register ct_pdr1_lsb_reg/ct_pdr2_lsb_reg (Programmable Divider Register Least
Significant Byte)
This configuration register is the least significant byte of a 16-bit counter used to define
the ETU.
This register is doubled: ct_pdr1_lsb_reg is dedicated to the full slot and ct_pdr2_lsb_reg
is dedicated to the auxiliary slot. Both registers share the same address, the selection is
done via bit IOauxen of register ct_ssr_reg.
Table 250. ct_pdr1_lsb_reg/ct_pdr2_lsb_reg (address 0004h) bit description
Bit Symbol Access
31:8 RESERVED -
7:0 PD7 - PD0 R/W
13.6.2.3 Register ct_pdr1_msb_reg/ct_pdr2_msb_reg (Programmable Divider Register Most
Significant Byte)
This configuration register is the most significant byte of a 16-bit counter used to define
the ETU.
This register is doubled: ct_pdr1_msb_reg is dedicated to the full slot and
ct_pdr2_msb_reg is dedicated to the auxiliary slot. Both registers share the same
address, the selection is done via bit IOauxen of register ct_ssr_reg.
Table 251. ct_pdr1_msb_reg/ct_pdr2_msb_reg (address 000Ch) bit description
Bit Symbol Access
31:8 RESERVED -
7:0 PD15 – PD8 R/W
The ETU (and also the card clock CLK) generation is shown by the following figure:
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Reset Description
Value
0 Reserved
0111 Least significant byte of a 16-bit counter defining the ETU. The ETU counter
0100b counts a number of cycles of the Contact Interface clock, this defines the ETU.
The minimum acceptable value is 0001 0000b.
Reset Description
Value
0 Reserved
0000 Most significant byte of a 16-bit counter defining the ETU. The ETU counter
0001b counts a number of cycles of the Contact Interface clock, this defines the ETU.
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Rev. 1.4 — 14 May 2018
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