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NXP Semiconductors
Name
HOSTIF_CLR_DATA_READY
_REG
HOSTIF_DATA_READY_STA
TUS_REG
HOSTIF_DBG_RX_REG
HOSTIF_DBG_RX_ADDR_R
EG
INTERNAL_USE
INTERNAL_USE
INTERNAL_USE
HOSTIF_INT_CLR_ENABLE_
REG
HOSTIF_INT_SET_ENABLE
_REG
HOSTIF_INT_STATUS_REG 3FE0h
HOSTIF_INT_ENABLE_REG 3FE4h
HOSTIF_INT_CLR_STATUS
_REG
14.3.5.2 Register description
HOSTIF_STATUS_REG
This register reflects the current status of the host Interface.
Table 323. HOSTIF_STATUS_REG (address offset 0x0000)
Bit
31:6
5
4
3
2
1
0
HOSTIF_CONTROL_REG
This register is used to control the buffer manager.
UM10858
User manual
COMPANY PUBLIC
Address
Width
Access
offset
(bits)
006Ch
32
W
0070h
32
R
0074h
32
R
0078h
32
R
007Ch
32
R/W
0080h
32
R
0084h
32
R/W
3FD8h
32
W
3FDCh
32
W
32
R
32
R
3FE8h
32
W
Symbol
Access
RESERVED
R
TX_BUFFER_PREFET
R
CH_OK
TX_BUFFER_LOCK
R
RX3_BUFFER_LOCK
R
RX2_BUFFER_LOCK
R
RX1_BUFFER_LOCK
R
RX0_BUFFER_LOCK
R
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
PN7462 family HW user manual
Reset
Description
value
00000000
Clear data ready flags for buffers
00000000
Status of data ready flags for buffers
00000000
Debug Received data
00000000
Debug receive address
00000000
For internal use
00000000
For internal use
000000Fh
For internal use
00000000
Clear interrupt enable
00000000
Set interrupt enable
00000000
Interrupt status
00000000
Interrupt enable
00000000
Clear interrupt
Value
Description
0
Reserved
0
1 - Read prefetch of TX buffer completed.
0
1 - TX buffer is currently in use by the
hardware.
1 - RX buffer 3 is currently in use by the
0
hardware.
0
1 - RX buffer 2 is currently in use by the
hardware.
0
1 - RX buffer 1 is currently in use by the
hardware.
1 - RX buffer 0 is currently in use by the
0
hardware.
UM10858
© NXP B.V. 2018. All rights reserved.
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