NXP Semiconductors PN7462 series User Manual page 248

NXP Semiconductors
14.1.9.17 INT_SET_STATUS_REG
This register is a collection of Set Interrupt Status commands. Writing 1 to this register
does set the corresponding Interrupt Request ENABLE flag. Writing 0 to this register has
no effect.
Table 292. INT_SET_STATUS_REG (address offset 0x3FEC)
Legend: * reset value; <= mandatory value
Bit Symbol
31:12
RESERVED
11
SET_STATUS_TX_FIFO_
THRES
10
SET_STATUS_RX_FIFO_
THRES
SET_STATUS_FIFO_EMP
9
TY
8 SET_STATUS_FIFO_FUL
L
7:4 RESERVED
SET_STATUS_I2C_BUS_
3
ERROR
SET_STATUS_NACK
2
1 SET_STATUS_ARB_FAIL
URE
0 SET_STATUS_TRN_COM
PLETED
14.1.10 Using example
14.1.10.1 I2C master transmitter example
Example with:
1. Slave address = 0x2A
2. 9 bytes to be transmitted
3. I2C clock frequency = 1 MHz
Step 1: Configure the I2C Master in Master Transmitter mode with an APB Write
Transaction using write data 0x0000000C at offset address 0x00000 {CONFIG_REG}.
Step 2: Configure the I2C slave address with an APB Write Transaction using write data
0x0000002A at offset address 0x0000C {I2C_ADDRESS_REG}.
Step 3: Configure the I2C clock frequency with an APB Write Transaction using write
data 0x00000000 at offset address 0x00004 {BAUDRATE_REG}.
Step 4: Configure the byte count with an APB Write Transaction using write data
0x00000009 at offset address 0x00014 {BYTECOUNT_CONFIG_REG}.
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User manual
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Access Value Description
R 0x0* reserved
Writing 1 to this register does set the corresponding IRQ
W 0x0*
STATUS flag
W 0x0*
Writing 1 to this register does set the corresponding IRQ
STATUS flag
W 0x0*
Writing 1 to this register does set the corresponding IRQ
STATUS flag
W 0x0*
Writing 1 to this register does set the corresponding IRQ
STATUS flag
R 0x0*
reserved
W 0x0*
Writing 1 to this register does set the corresponding IRQ
STATUS flag
W 0x0*
Writing 1 to this register does set the corresponding IRQ
STATUS flag
W 0x0*
Writing 1 to this register does set the corresponding IRQ
STATUS flag
Writing 1 to this register does set the corresponding IRQ
W 0x0*
STATUS flag
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
UM10858
PN7462 family HW user manual
© NXP B.V. 2018. All rights reserved.
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