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14.1.7 External wiring
The I2C controller operates on an external clock. For proper operation, external blocks
must supply a clock signal to the apb_clk pin. Furthermore, as can be seen in
analog characteristics of the I2C bus (data and clock are connected to pull-up resistors)
cause that the SCL and SDA lines must be driven by a pull-down circuit also called "I2C".
The signals scl_out and sda_out are then used to enable the pull-down circuit (when '0')
or disable it when '1'.
14.1.8 I2C Register overview
Table 275. I2CM Register overview (base address 0x4003 0000)
Name
CONFIG_REG
[1]
BAUDRATE_REG
[1]
SDA_HOLD_REG
[1]
I2C_ADDRESS_REG
[1]
FIFO_THRESHOLD_REG
BYTECOUNT_CONFIG_REG
UM10858
User manual
COMPANY PUBLIC
Fig 45. I2C external wiring diagram
Address
Width
Access
offset
(bits)
0x0000
32
RW
0x0004
32
RW
0x0008
32
RW
0x000C
32
RW
0x0010
32
RW
0x0014
32
RW
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
Reset value
Description
0x00000000
Register fields to configure the I2C Master &
I2C (Transmission/Reception) mode of
operation.
0x000000F4
Register field to generate the I2C Serial Clock
Frequency. Default: 1 MHz Serial Clock
Frequency at input system/IP Clock
Frequency of 27 MHz
0x00000009
Used to set the SDA hold time (SDA
generation with respect to falling edge on
SCL) - Must be set to 0x00 when operating in
Fast-mode Plus (freq SCL> 400 kHz)
0x0000002A
Contains the I2C Slave address of the device.
0x00000701
Register field to set the FIFO Threshold Level
for the Interrupt Request Generation
0x00000000
Register bit field to configure the number of
bytes to be transmitted or received
314514
UM10858
PN7462 family HW user manual
Fig
© NXP B.V. 2018. All rights reserved.
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