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NXP Semiconductors
Table 238. CLIF_INT_SET_ENABLE_REG register (address 3FDCh)
* = reset value
Bit
Symbol
31:30
RESERVED
29
AGC_RFOFF_DET_
IRQ_SET_ENABLE
28
TX_DATA_REQ_IRQ_SET_E
NABLE
RX_DATA_AV_IRQ_SET_EN
27
ABLE
26
RX_BUFFER_OVERFLOW_I
RQ_SET_ENABLE
25
TX_WATERLEVEL_IRQ_SET
_ENABLE
24
RX_WATERLEVEL_IRQ_SET
_ENABLE
23
RESERVED
22
RX_SC_DET_IRQ_SET_ENA
BLE
21
RX_SOF_DET_IRQ_SET_EN
ABLE
20
RX_EMD_IRQ_SET_ENABLE W
19
TIMER3_IRQ_SET_ENABLE
18
TIMER2_IRQ_SET_ENABLE
17
TIMER1_IRQ_SET_ENABLE
16
TIMER0_IRQ_SET_ENABLE
15
CLOCK_ERROR_IRQ_SET_
ENABLE
[1]
14
INTERNAL_USE
[1]
13
INTERNAL_USE
12
RF_ACTIVE_ERROR_IRQ_S
ET_ENABLE
11
TX_RFON_IRQ_SET_ENABL
E
10
TX_RFOFF_IRQ_SET_ENAB
LE
9
RFON_DET_IRQ_SET_ENAB
LE
8
RFOFF_DET_IRQ_SET_ENA
BLE
7:6
RESERVED
UM10858
User manual
COMPANY PUBLIC
Access
Value
Description
W
0
Reserved
W
0, 1
Writing 1 to this register does set the corresponding IRQ
ENABLE flag
W
0, 1
Writing 1 to this register does set the corresponding IRQ
ENABLE flag
Writing 1 to this register does set the corresponding IRQ
W
0, 1
ENABLE flag
W
0, 1
Writing 1 to this register does set the corresponding IRQ
ENABLE flag
W
0, 1
Writing 1 to this register does set the corresponding IRQ
ENABLE flag
W
0, 1
Writing 1 to this register does set the corresponding IRQ
ENABLE flag
W
0
Reserved
W
0, 1
Writing 1 to this register does set the corresponding IRQ
ENABLE flag
W
0, 1
Writing 1 to this register does set the corresponding IRQ
ENABLE flag
0, 1
Writing 1 to this register does set the corresponding IRQ
ENABLE flag
W
0, 1
Writing 1 to this register does set the corresponding IRQ
ENABLE flag
W
0, 1
Writing 1 to this register does set the corresponding IRQ
ENABLE flag
W
0, 1
Writing 1 to this register does set the corresponding
W
0, 1
Writing 1 to this register does set the corresponding IRQ
ENABLE
W
0, 1
Writing 1 to this register does set the corresponding IRQ
ENABLE
W
0, 1
For internal use
W
0, 1
For internal use
W
0, 1
Writing 1 to this register does set the corresponding IRQ
ENABLE flag
W
0, 1
Writing 1 to this register does set the corresponding IRQ
ENABLE flag
W
0, 1
Writing 1 to this register does set the corresponding IRQ
ENABLE flag
W
0, 1
Writing 1 to this register does set the corresponding IRQ
ENABLE flag
W
0, 1
Writing 1 to this register does set the corresponding IRQ
ENABLE flag
W
0
Reserved
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
UM10858
PN7462 family HW user manual
© NXP B.V. 2018. All rights reserved.
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