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NXP Semiconductors
HOSTIF_I2C_CONTROL_REG
This register is used is to control the I²C host interface.
Table 326. HOSTIF_I2C_CONTROL_REG (address offset 0x000C)
Bit
31:8
7:5
4
3
2
1:0
HOSTIF_SPI_CONTROL_REG
This register is used to control the SPI host interface.
Table 327. HOSTIF_SPI_CONTROL_REG (address offset 0x0010)
Bit
31:2
1
0
HOSTIF_HSU_CONTROL_REG
This register is used to control the High-speed UART host interface
Table 328. HOSTIF_HSU_CONTROL_REG (address offset 0x0014)
Bit
31:28
27:21
20
19:18
17:16
UM10858
User manual
COMPANY PUBLIC
Symbol
Access
RESERVED
R
I2C_REV_ID
R/W
I2C_DEVID_ENABLE
R/W
I2C_RESET_ENABLE
R/W
I2C_HS_ENABLE
R/W
I2C_ADDR
R/W
Symbol
Access
RESERVED
R
SPI_CPHA
R/W
SPI_CPOL
R/W
Symbol
Access
RESERVED
R
HSU_EOF_SIZE
R/W
HSU_STORE_BR_BY
R/W
TE
HSU_BR_ESTIMATOR
R/W
_MODE
HSU_WAKEUP_BYTE
R/W
S
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
PN7462 family HW user manual
Reset
Description
Value
0
Reserved
0
Die Revision of Device ID
0
1 - Enable Device ID defined in the I2C
standard
0
1 - Enable Soft Reset sequence defined in
the I2C standard
0
1 - Enable High-speed mode
0
Set two LSBs of the I2C address
Reset
Description
Value
0
Reserved
0
SPI clock phase
0
SPI clock polarity
Reset
Description
Value
0
Reserved
0x10
EOF duration in bit number - 1 (1-122)
0
1: the first 0 used to estimate baud rate is
stored in memory
0
00: Baud rate estimator inactive
01: Baud rate estimator active with
automatic clock setting
10: Baud rate estimator active without
clock setting
11: Reserved
1
Number of bytes lost during wakeup at
RTS rising edge
UM10858
© NXP B.V. 2018. All rights reserved.
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