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NXP Semiconductors
14.2.9.13 SPIM_INT_STATUS_REG
This register is a collection of Interrupt Status commands. Writing 1 to this register does
set the corresponding Interrupt Request ENABLE flag. Writing 0 to this register has no
effect.
Table 307. SPIM_INT_STATUS_REG (address offset 0x3FE0)
Bit
31:10
9
8
7:3
2
1
0
14.2.9.14 SPIM_INT_ENABLE_REG
This register is a collection of Interrupt Enable commands. Writing 1 to this register does
set the corresponding Interrupt Request ENABLE flag. Writing 0 to this register has no
effect.
Table 308. SPIM_INT_ENABLE_REG (address offset 0x3FE4)
Bit
31:10
9
8
7:3
2
1
0
14.2.9.15 SPIM_INT_CLR_STATUS_REG
This register is a collection of Clear Interrupt Status commands. Writing 1 to this register
does set the corresponding Interrupt Request ENABLE flag. Writing 0 to this register has
no effect.
Table 309. SPIM_INT_CLR_STATUS_REG (address offset 0x3FE8)
Bit
31:10
UM10858
User manual
COMPANY PUBLIC
Symbol
RESERVED
AHB_ADDR_ERROR_STAT
US
AHB_ERROR_STATUS
RESERVED
WATERLEVEL_REACHED_S
TATUS
EOT_STATUS
EOR_STATUS
Symbol
RESERVED
AHB_ADDR_ERROR_ENAB
LE
AHB_ERROR_ENABLE
RESERVED
WATERLEVEL_REACHED_E
NABLE
EOT_ENABLE
EOR_ENABLE
Symbol
RESERVED
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
PN7462 family HW user manual
Access Reset
Description
Value
R
0
Reserved
R
0
AHB address overflow Error interrupt
status
R
0
AHB Slave Error interrupt status
R
0
Reserved
R
0
Water level reached interrupt status
R
0
EOT interrupt status
R
0
EOR interrupt status
Access Reset
Description
Value
R
0
Reserved
R
0
AHB address overflow Error interrupt
enable
R
0
AHB Slave Error interrupt enable
R
0
Reserved
R
0
Water level reached interrupt enable
R
0
EOT interrupt enable
R
0
EOR interrupt enable
Access Reset
Description
Value
W
0
Reserved
UM10858
© NXP B.V. 2018. All rights reserved.
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