Register Overview And Functions - NXP Semiconductors PN7462 series User Manual

NXP Semiconductors

15.4 Register overview and functions

This section gives an overview of the register set used to control the hardware
functionalities of the USB full speed device controller.
15.4.1 Register overview
Table 355. Register overview (base address 0x4002 8000)
Address Register name
offset
0x00 USB device Command/Status
register
0x04 USB Info register
0x08 USB Endpoint List start address
0x0C USB Data Buffer start address
0x10 USB Link Power Management
0x14 USB EP skip
0x18 USB EP Buffer in use
USB EP Buffer configuration
0x1C
register
0x20 USB Interrupt status register
0x24 USB Interrupt enable register
0x28 USB Set Interrupt status register
0x2C USB Interrupt routing register
0x30 USB configuration
0x34 USB EP toggle
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Access Description
R/W (C) This register contains all the fields to control the behavior of
the USB device
RO This register contains the frame number of the last received
SOF, the ChipID and the error code
R/W This register contains the start address of the endpoint list that
are stored in memory.
R/W This register contains the start address of the endpoint data
buffers in memory
R/W This register contains the fields for the link power management
support
R/W This register is used to indicate to hardware that it has to
deactivate the corresponding endpoint (set active bit to zero)
R/W This bit is used for double buffering. It indicates which buffer is
in-use for each endpoint
This bit indicates if the endpoint has single buffering or double
R/W
buffering
R/W This register contains the status bits of the different interrupts
This register contains the enable bits of the different interrupts.
R/W
If this bit is set and the corresponding interrupt status bit is set
a hardware interrupt is generated
R/W If '1' is written to one of the bits of this register, the
corresponding interrupt status bit is set to one. When this
register is read, it returns the same value as the USB Interrupt
status register
R/W Each interrupt bit has a corresponding interrupt routing bit. If
the interrupt routing bit is set to zero, a hardware interrupt will
be generated on the IRQ line if both the corresponding
interrupt status and interrupt enable bits are set.
If the interrupt routing bit is set to one, a hardware interrupt is
generated on the FIQ line if both the corresponding interrupt
status and interrupt enable bits are set
RO This contains the configuration values as specified in section 6
(R&D document)
RO This debug register is used to indicate the current data toggle
value of the corresponding endpoint
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
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