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NXP Semiconductors
Bit
Symbol
21
RX_SOF_DET_IRQ
20
RX_EMD_IRQ
19
TIMER3_IRQ
18
TIMER2_IRQ
17
TIMER1_IRQ
16
TIMER0_IRQ
15
CLOCK_ERROR_IRQ
[1]
14
INTERNAL_USE
[1]
13
INTERNAL_USE
12
RF_ACTIVE_ERROR_IRQ
11
TX_RFON_IRQ
10
TX_RFOFF_IRQ
9
RFON_DET_IRQ
8
RFOFF_DET_IRQ
7:6
RESERVED
5
STATE_CHANGE_IRQ
4
CARD_ACTIVATED_IRQ
3
MODE_DETECTED_IRQ
2
IDLE_IRQ
1
TX_IRQ
0
RX_IRQ
[1]
Bit-field are either set by HAL or use default value from CLIF EEPROM default settings
Table 240. CLIF_INT_ENABLE_REG register (address 3FE4h)
* = reset value
Bit
Symbol
31:30
RESERVED
29
AGC_RFOFF_DET_
IRQ_ENABLE
28
TX_DATA_REQ_IRQ_ENABL
E
UM10858
User manual
COMPANY PUBLIC
Access
Value
Description
R
0*, 1
Set to 1 by hardware, when in reader mode an SOF is
detected
R
0*, 1
Set to 1 by hardware, when an EMD event is detected
R
0*, 1
Set to 1 by hardware, when the Timer3 is expired.
R
0*, 1
Set to 1 by hardware, when the Timer2 is expired.
R
0*, 1
Set to 1 by hardware, when the Timer1 is expired.
R
0*, 1
Set to 1 by hardware, when the Timer0 is expired.
Set to 1 by hardware, when RF-Field vanished (and
R
0*, 1
consequently the RF-Clock is not present) and the clock of
the system PLL is not available
R
0*, 1
For internal use
R
0*, 1
For internal use
R
0*, 1
Set to 1 by hardware, when an RF error case occurred
R
0*, 1
Set to 1 by hardware, when the internally generated RF-
field was switched on.
R
0*, 1
Set to 1 by hardware, when the internally generated RF-
field was switched off.
R
0*, 1
Set to 1 by hardware, when an external RF-field is detected.
R
0*, 1
Set to 1 by hardware, when an external RF-field is
switched off.
R
0
Reserved
R
0*, 1
Set to 1 by hardware, when a transceive state is entered
selected in the register field STATE_TRIGGER_SELECT
R
0*, 1
Set to 1 by hardware, when TypeA card mode activation
FSM reached the ACTIVATED or ACTIVATE_S state
R
0*, 1
Set to 1 by hardware, when the card mode has been
detected by the ModeDetector
Note: While the TypeA activation FSM is active no IRQ is
issued any more
R
0*, 1
Set to 1 by hardware, when the IDLE state is entered
R
0*, 1
Set to 1 by hardware, when an ongoing transmission is
finished.
R
0*, 1
Set to 1 by hardware, when an ongoing reception is
finished
Access
Value
Description
R
0
Reserved
R
0, 1
If this bit is 1 the corresponding IRQ can propagate to the
CPUs IRQ controller
R
0*, 1
If this bit is 1 the corresponding IRQ can propagate to the
CPUs IRQ controller
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
UM10858
PN7462 family HW user manual
© NXP B.V. 2018. All rights reserved.
191 of 345
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