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NXP Semiconductors
Bit
Symbol
1
SUSPEND_INT_SET_STAT
US
0
GPIO_INT_SET_STATUS
9. CRC
This block implements a configurable 16/32-bit parallel CRC.
The 16-bit CRC is compliant to X.25 (CRC-CCITT, ISO/IEC13239) standard with a
generator polynomial of:
x g
The 32-bit CRC is compliant to the Ethernet / AAL5 (IEEE 802.3) standard with a
generator polynomial of:
x g
Note: No final XOR is performed.
CRC calculation is performed in parallel, meaning that one CRC calculation is performed
in one clock cycle.
The standard CRC32 polynomial passes the fips140-2 tests.
9.1 CRC features
• Configurable CRC preset value
• Selectable LSB or MSB first
• Calculation based on 32 bits, 16 bits, 8 bits words
9.2 Parallel CRC
In parallel CRC calculation, each bit of the new CRC depends on the previous bits of the
CRC and current bits of the input data. Using mathematical assumptions, one equation
can be calculated for each bit of the new CRC which are derived from the serial CRC
implementation. Using these equations, a CRC can be calculated in one clock cycle
whereas serial CRC takes as many clock cycles as the number of bits in the CRC.
UM10858
User manual
COMPANY PUBLIC
Access
Value
-x
0x00
-x
0x00
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26
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All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
Description
Suspend interrupt set status.
1: Set suspend (exit) interrupt. Auto clear after 2 cycles.
GPIO interrupt clear status
1: Set GPIO interrupt. Auto clear after 2 cycles.
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UM10858
PN7462 family HW user manual
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© NXP B.V. 2018. All rights reserved.
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