NXP Semiconductors PN7462 series User Manual page 159

NXP Semiconductors
Bit Symbol
[1]
1 INTERNAL_USE
0 INITIATOR
[1] Bit-field are either set by HAL or use default value from CLIF EEPROM default settings
Table 190. CLIF_TX_WAIT_REG register (address 0010h)
* = reset value
Bit Symbol
31:28 RESERVED
27:8 TX_WAIT_VALUE
7:0 TX_WAIT-
PRESCALER
Table 191. CLIF_RX_WAIT_REG register (address 0018h)
* = reset value
Bit Symbol
31:28 RESERVED
27:8 RX_WAIT_VALUE
7:0 RX_WAIT-
PRESCALER
Table 192. CLIF_TX_WATERLEVEL_REG register (address 0024h)
* = reset value
Bit Symbol
31:8 RESERVED
7:0 TX_WATERLEVEL
UM10858
User manual
COMPANY PUBLIC
Access Value
D 0*, 1
R/W 0*, 1
Access Value
R 0
D 0* - FFFFFh
D 0*-FFh
Access Value
R 0
R/W 0* - FFFFFh
R/W 0*-FFh
Access Value
R 0
R/W 0* - 0xFF
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
PN7462 family HW user manual
Description
for internal use
Set to 1, the CLIF is configured for initiator mode. Depending
on this setting the behavior of the transceive command is
different
Description
Reserved
Defines the tx_wait timer reload value.
Note: If set to 00000h the tx_wait guard time is
Disabled
Note: This bit is set by HW a protocol is detected in
automatic mode detection
Defines the prescaler reload value for the tx_wait
timer.
Note: This bit is set by HW a protocol is detected in
automatic mode detection
Description
Reserved
Defines the rx_wait timer reload value.
Note: If set to 00000h the rx_wait guard time is
Disabled
Defines the prescaler reload value for the Rx_wait
timer.
Description
Reserved
Defines a warning level to indicate that TX_WATERLEVEL
number of words were already transmitted in the actual
frame. When this level is reached the corresponding IRQ is
set.
Note: 0 disables the water level
Note: In case a header byte offset is set the water level
refers to word fetched from RAM
UM10858
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