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NXP Semiconductors
HOSTIF_BUFFER_RX<n>_CFG_REG.RX<n>_START_ADDR. The memory address is
incremented after a word has been received. The address is only incremented internally
meaning that the memory start address is not changed.
The RX buffers can be labelled to receive either non-short frames or short frames
depending on the value of bit
HOSTIF_BUFFER_RX<n>_CFG_REG.RX<n>_SHORT_FRAME_BUFFER. This is not
applicable to the Native Mode.
HOSTIF_BUFFER_RX<n>_CFG_REG.RX<n>_HEADER_OFFSET defines the number
of padding bytes to add to the frame header before writing the first word to the RX buffer.
By default, this value is set to 2 since the standard HDLL header is 2 bytes long. Since
the minimum length of the header is 2 bytes, an offset of 3 is not permitted since
this would result in the header being stored across the first two words in the
buffer.
TX buffer
There is no explicit disable field in register HOSTIF_BUFFER_TX_CFG_REG since the
TX buffer is effectively disabled when
HOSTIF_DATA_READY_STATUS_REG.TX_DATA_READY is cleared to logic low.
The TX buffer must be configured with the following parameters, which are defined in
HOSTIF_BUFFER_TX_CFG_REG:
• Start address
• Header offset
• Empty payload enable
The start address bit 0-14 is defined in field
HOSTIF_BUFFER_TX_CFG_REG.TX_START_ADDR.
Base address is fix in SRAM (address 0x100000).
The header offset is defined in field
HOSTIF_BUFFER_TX_CFG_REG.TX_HEADER_OFFSET. It states the number of bytes
to skip before sending them to the Host Interface Core
To configure the buffer manager to send only the header and its calculated CRC, set
HOSTIF_BUFFER_TX_CFG_REG.TX_EMPTY_PAYLOAD_ENABLE to logic high.
This is not applicable to native mode.
14.3.4.2 HDLL format
The HDLL frame format is shown in
written to SRAM. The CRC is not written.
UM10858
User manual
COMPANY PUBLIC
Fig
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
PN7462 family HW user manual
66. Both the HDLL header and payload are
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