NXP Semiconductors PN7462 series User Manual page 221

NXP Semiconductors
13.6.2.8 Register ct_ccr1_reg/ct_ccr2_reg (Clock Configuration Register)
This configuration register defines the card clock frequency.
This register is doubled: ct_ccr1_reg is dedicated to the full slot (card 1) and ct_ccr2_reg
is dedicated to the auxiliary slot (card 2). Both registers share the same address, the
selection is done via bit IOauxen of register ct_ssr_reg.
Table 256. ct_ccr1_reg/ct_ccr2_reg (address 001Ch) bit description
Bit Symbol Access
31:6 RESERVED -
5 FIP R/W
4 CST R/W
3 SAN R/W
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Reset Description
Value
0 reserved
0b Stop HIGH or LOW
- Slot 1:
If bits SAN = 0 and CST = 1, then the clock is stopped at LOW level if bit SHL =
0, and at HIGH level if bit SHL = 1.
If bit SAN = 1, then contact CLK is the copy of the value of bit SHL.
- Slot AUX:
If bits SAN = 0 and CLKAUXen = 0, then the clock is stopped at LOW level if bit
SHL = 0, and at HIGH level if bit SHL = 1 (CLKAUX output is inverted). SHL bit
value should not change while CLKAUXen = 1: dynamic change is not
supported. SHL bit value should be chosen before enabling CLKAUX clock with
CLKAUXen bit.
If bit SAN = 1, then contact CLKAUX is the copy of the value of bit SHL.
0b Clock STop
- Slot 1:
In the case of an asynchronous card, bit CST defines whether the clock to the
card is stopped or not; if bit CST is reset to logic 0, then the clock is determined
by bits ACC0, ACC1 and ACC2.
- Slot AUX:
This bit is not available for the auxiliary slot (ct_ccr2_reg) since clock stop
feature is supported using CLKAUXen bit in ct_ssr_reg register.
0b Synchronous/Asynchronous Card
- Slot 1:
When set to logic 1, the Contact UART supports synchronous card. The
Contact UART is then bypassed, only bit 0 of registers ct_urr_reg and
ct_utr_reg is connected to pin I/O. In this case, the card clock is controlled by
bit SHL and RST card is controlled by bit RSTIN in register ct_pcr_reg. When
set to logic 0, the Contact UART supports asynchronous card. Dynamic change
(while activated) is not supported. The choice should be done before activating
the card.
- Slot AUX:
When set to logic 1, the Contact UART supports synchronous card. The
Contact UART is then bypassed, only bit 0 of registers ct_urr_reg and
ct_utr_reg is connected to pin I/O. In this case, the card clock is controlled by
bit SHL. When set to logic 0, the Contact UART supports asynchronous card.
Dynamic change (while CLKAUXen = 1) is not supported. The choice should be
done before enabling CLKAUX clock.
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Rev. 1.4 — 14 May 2018
314514
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