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14.3.4.13 TX frame not available
If there is no data ready to be sent in the transmit buffer (bit TX_DATA_READY in
register HOSTIF_DATA_READY_STATUS_REG is logic low) when the Host Interface
Core Asserts Data Request, the Buffer Manager sets
TX_FRAME_NOT_AVAILABLE_STATUS in register HOSTIF_INT_STATUS_REG and
asserts the corresponding output logic high. The output will remain logic high until the
firmware sets TX_FRAME_NOT_AVAILABLE_CLR_STATUS in register
HOSTIF_INT_CLR_STATUS_REG.
For I2C: if the host reads a 1st data while no buffer is available, data will be NACKed and
no IRQ will be raised.
For SPI: if the host reads a 1st data while no buffer is available, 0xff will be sent and no
IRQ will be raised.
For HSUART: not applicable since the host interface is master of HSUART TX
transaction.
14.3.4.14 TX Inter-Character (TIC) timeout
The TX Inter-Character (TIC) timer is used to measure the delay between sending
characters. The following features are implemented:
• Programmable timeout
• Timer is reloaded with the value in
• HOSTIF_TIC_TIMEOUT_REG.TX_TIMEOUT_VALUE after the transmission of each
• Automatic start of timer after first character has been transmitted
• Automatic stop of timer after number of transmitted bytes is equal to the frame
• Timeout range 200 ms with a granularity of 5 us
A divide-by-100 prescaler divides down the high frequency oscillator clock in order to
generate a 3.6us tick. This tick clocks the 16-bit TIC timer, whose initial value is specified
in field TX_TIMEOUT_VALUE of register HOSTIF_TIC_TIMER_REG.
This field must be loaded with a non-zero value. Since the power-on-reset value is
zero, the TIC timer is disabled by default.
The TIC counter will only start decrementing when
HOSTIF_DATA_READY_STATUS_REG.TX_DATA_READY=1 (this is to avoid the case
where the host attempts to read an empty buffer).
If the TIC timer expires during transmission, the buffer manager sets
TX_TIMEOUT_STATUS in register HOSTIF_INT_STATUS_REG. The buffer manager
also clears bit HOSTIF_DATA_READY_STATUS_REG.TX_DATA_READY logic low to
abort the frame transmission
The firmware is responsible for re-sending the frame in the event of a TIC timeout
by setting once again HOSTIF_SET_DATA_READY_REG.SET_TX_DATA_READY.
This will cause the Buffer Manager to initiate a new read prefetch sequence. An EOT
event is not generated. The EOT_STATUS flag in register HOSTIF_INT_STATUS_REG
UM10858
User manual
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length.
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Rev. 1.4 — 14 May 2018
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UM10858
PN7462 family HW user manual
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