NXP Semiconductors PN7462 series User Manual page 225

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NXP Semiconductors
Bit
Symbol
Access
3:2
clk_sr1 -
R/W
clk_sr0
1:0
io_sr1 - io_sr0
R/W
13.6.2.16 Register ct_urr_reg/ct_utr_reg (UART Receive Register/UART Transmit Register)
These two data registers share the same address but the first one can only be read and
the second only be written. They constitute the access to the Contact UART FIFO
respectively in reception and transmission modes.
Table 264. ct_urr_reg/ct_utr_reg (address 003Ch, 0040h, 0044h, 0048h) bit description
Bit
Symbol
Access
31:0
URR31 - URR0 R
31:0
UTR31 - UTR0
W
UM10858
User manual
COMPANY PUBLIC
Reset
Description
Value
Dynamic change (while activated) is not supported. The choice"
should be done before activating the card.
00b
CLK slew rate
Card clock slew rate selection.
00b
I/O slew rate
Card I/O slew rate selection.
Reset
Description
Value
0000
Uart Receive Register
0000h
Asynchronous card:
When the controller wants to read a character from the card stored into the
FIFO, it reads it from this register in direct convention.
- In case of byte access (bit wrdacc = 0 in register ct_ucr2_reg), the byte is
read on the 8 least significant bits:
URR31 - URR8: 000000h (unvalid bytes)
URR7 - URR0: byte (received byte)
- In case of word access (bit wrdacc = 1 in register ct_ucr2_reg), 4 characters
are read:
URR31 - URR24: byte 4 (last received byte)
URR23 - URR16: byte 3
URR15 - URR8: byte 2
URR7 - URR0: byte 1 (first received byte)
If less than 4 bytes are present into the FIFO, the missing bytes are read 00h
or previous values and interrupt bit wdraccerr in register ct_usr2_reg is set to
logic 1.
Synchronous card:
In reception mode, the data from the card is available to bit UR0 after a read
operation of register ct_urr_reg; the FIFO is bypassed.
0000
Uart Transmit Register
0000h
Asynchronous card:
When the micro-controller wants to transmit a character to the card, it writes
the byte in direct convention in the utr register (this byte will be stored into the
FIFO).
- In case of byte access (bit wrdacc = 0 in register ct_ucr2_reg), 1 byte is
written into the FIFO:
UTR31 - UTR8: 000000h (unused bytes)
UTR7 - UTR0 : byte (byte to transmit)
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
UM10858
PN7462 family HW user manual
© NXP B.V. 2018. All rights reserved.
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