NXP Semiconductors PN7462 series User Manual page 328

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NXP Semiconductors
15.4.2.6 USB Endpoint skip
Table 361. USB Endpoint skip (address offset = 0x14)
Reset value: 0x00000000
Bit
Symbol
Description
29:0
SKIP
Endpoint skip: Writing „1 to one of these bits, will indicate to hardware that it
must deactivate the buffer assigned to this endpoint and return control back to
firmware. When hardware has deactivated the endpoint it will clear this bit. But it
will not modify the "Buffer in use" bit. An interrupt will be generated when the
Active bit goes from „1‟ to „0‟.
Note: In case of double buffering, hardware will only clear the Active bit of the
buffer indicated by the "Buffer in use" bit.
31:30 RESERVE
Reserved
D
15.4.2.7 USB Endpoint Buffer in use
Table 362. USB Endpoint Buffer in use (address offset = 0x18)
Reset value: 0x00000000
Bit
Symbol
1:0
-
29:2
BUF
31:30 RESERVED
15.4.2.8 USB Endpoint Buffer Configuration
Table 363. USB Endpoint Buffer Configuration (address offset = 0x1C)
Reset value: 0x00000000
Bit
Symbol
Value
1:0
RESERVED 0
29:2
BUF_SB
0
1
31:30 RESERVED
UM10858
User manual
COMPANY PUBLIC
Value
Description
Reserved
Buffer in use – This bit has one bit per physical endpoint
0
hardware is accessing buffer 0
1
hardware is accessing buffer 1
Reserved
Description
Reserved. Fixed to zero because the control endpoint zero is fixed to
single buffering for each physical endpoint.
Buffer usage – This bit has one bit per physical endpoint. If the bit is
set to single buffer („0‟), it will not toggle the corresponding "USB EP
Buffer in use" bit when it clears the active bit.
If the bit is set to double buffer („1‟), hardware will toggle the "USB EP
Buffer in use" bit when it clears the Active bit for the buffer.
Single buffer
Double buffer
Reserved
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
UM10858
PN7462 family HW user manual
Reset
Access
Value
0
R/W
0
RO
Reset
Value
0
0
0
Reset
Value
0
0
0
© NXP B.V. 2018. All rights reserved.
Access
RO
R/W
RO
Access
RO
R/W
RO
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