NXP Semiconductors PN7462 series User Manual page 93

NXP Semiconductors
Bit Symbol
Table 86. PCR_PADIN_REG (address offset 0x38)
Bit Symbol
31:28 RESERVED
27 RESERVED
26 PADIN_CLK_AUX
25 PADIN_IO_AUX
24 PADIN_INT_AUX
23 PADIN_GPIO12
22 PADIN_GPIO11
21 PADIN_GPIO10
20 PADIN_GPIO9
19 PADIN_GPIO8
18 PADIN_GPIO7
17 PADIN_GPIO6
16 PADIN_GPIO5
15 PADIN_GPIO4
14 PADIN_GPIO3
13 PADIN_GPIO2
12 PADIN_GPIO1
11 PADIN_DWL_REQ
10 PADIN_MISO_M
9 PADIN_MOSI_M
8 PADIN_SCLK_M
7 PADIN_NSS_M
6 PADIN_SDA_M
5 PADIN_SCL_M
4 PADIN_IRQ
3 PADIN_ATX_D
2 PADIN_ATX_C
1 PADIN_ATX_B
0 PADIN_ATX_A
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Access Value Description
01: DIVby2
10: DIVby4
11: Reserved
Access Value Description
- 0x00 Reserved
r- 0x00 Reserved
r- 0x00 input value for CLK_AUX
r- 0x00 input value for IO_AUX
r- 0x00 input value for INT_AUX
r- 0x00 input value for GPIO12
r- 0x00 input value for GPIO11
r- 0x00 input value for GPIO10
r- 0x00 input value for GPIO9
r- 0x00 input value for GPIO8
r- 0x00 input value for GPIO7
r- 0x00 input value for GPIO6
r- 0x00 input value for GPIO5
r- 0x00 input value for GPIO4
r- 0x00 input value for GPIO3
r- 0x00 input value for GPIO2
r- 0x00 input value for GPIO1
r- 0x00 input value for DWL_REQ
r- 0x00 input value for MISO_M
r- 0x00 input value for MOSI_M
r- 0x00 input value for SCLK_M
r- 0x00 input value for NSS_M
r- 0x00 input Value SDA_M
r- 0x00 input Value SCL_M
r- 0x00 input value for IRQ
r- 0x00 input Value ATX_D
r- 0x00 input Value ATX_C
r- 0x00 input Value ATX_B
r- 0x00 input Value ATX_A
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Rev. 1.4 — 14 May 2018
314514
UM10858
PN7462 family HW user manual
© NXP B.V. 2018. All rights reserved.
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