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NXP Semiconductors
PAD Name
MISO_M, MOSI_M, SCLK_M, NSS_M
SCL_M, SDA_M
GPIO1 to GPIO12
SWDIO, SWDCLK
IRQ
8.6.1 Hard Power Down (HPD) State of Pads
In the Hard Power Down mode, all digital pad signals will be masked.
8.6.2 Pad state in absence of PVDD
In absence of PVDD all input and output drivers will be disabled with a gate and all input
signals from the PAD will be clamped.
8.6.3 Selecting host interface
The PN7462 family connects to host through four pads: ATX_A/ATX_B/ATX_C/ATX_D.
There are three protocols by which PN7462 family connects to host through pads:
I2C/high-speed-UART/SPI. The selection of which protocol to connect with is done by
using configuration of PCR_SYS_REG.hif_selection bits in PCR_SYS_REG register
described in
8.7 Register overview
Table 71. Register overview (base address 0x4002 4000)
Name
PCR_GPREG0_REG
PCR_GPREG1_REG
PCR_GPREG2_REG
PCR_SYS_REG
PCR_PMU_REG
PCR_RFLD_REG
PCR_TEMP_REG
PCR_HOSTIF_WAKEUP_CF
G_REG
PCR_WAKEUP_CFG_REG
PCR_GPIO_WAKEUP_CFG_
REG
UM10858
User manual
COMPANY PUBLIC
Table
75.
Address
Width
Access
(bits)
Offset
0x0000
32
rw-
0x0004
32
rw-
0x0008
32
rw-
0x000c
32
rw-
0x0010
32
rw-
0x0014
32
rw-
0x0018
32
rw-
0x001c
32
rw-
0x0020
32
rw-
0x0024
32
rw-
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
PN7462 family HW user manual
Power Supply
PVDD_IN_M
PVDD_IN_M
PVDD_IN
PVDD_IN
PVDD_IN
Reset value
Description
0x00000000
General-purpose register 0 for SW
0x00000000
General-purpose register 1 for SW
0x00000000
General-purpose register 2 for SW
system configuration like Hostif selection
0x00000100
and CT enabling
PMU interface. For LDO, bandgap,
DC-to-DC converter configuration and
0x0217010C
sequences
0x00004032
CLIF configuration
temperature sensor calibration
0x00058888
information
configuring wake-up source for standby
0x00000000
and Suspend
configuring wake-up source for standby
0x00000000
and Suspend
configuring wake-up source for standby
0x000000FF
and suspend
UM10858
© NXP B.V. 2018. All rights reserved.
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