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NXP Semiconductors
Table 248. Register bit overview
Name
Access
Bit 7
ssr
R/W
RESERV
ED
pdr
R/W
PD7
LSB[2]
pdr
R/W
PD15
MSB[2]
Fcr
R/W
PEC2
gtr[2]
R/W
GT7
ucr1[2]
R/W
RESERV
ED
ucr2[2]
R/W
wrdacc
RESERV
ccr[2]
R/W
ED
pcr
R/W
C8
ecr
R/W
EC7
mcrl
R/W
MCL7
LSB
mcrl
R/W
MCL15
MSB
mcrh
R/W
MCH7
LSB
mcrh
R/W
MCH15
MSB
srr
R/W
RESERV
ED
urr[3]
R
UR7
utr[3]
W
UT7
tor1
W
TOL7
tor2
W
TOL15
tor3
W
TOL23
toc
R/W
TOC7
fsr
R
RESERV
ED
UM10858
User manual
COMPANY PUBLIC
Bit 6
Bit 5
Bit 4
RESERV
RESERV
pres con
ED
ED
no
PD6
PD5
PD4
PD14
PD13
PD12
PEC1
PEC0
ftc4
GT6
GT5
GT4
RESERV
FIP
FC
ED
FIFO
disintaux
disATR
flush
counter[4]
RESERV
SHL
CST[5]
ED
C4
RESERV
RSTIN
ED
EC6
EC5
EC4
MCL6
MCL5
MCL4
MCL14
MCL13
MCL12
MCH6
MCH5
MCH4
MCH14
MCH13
MCH12
RESERV
vcc rise
vcc rise
ED
sel1
sel0
UR6
UR5
UR4
UT6
UT5
UT4
TOL6
TOL5
TOL4
TOL14
TOL13
TOL12
TOL22
TOL21
TOL20
TOC6
TOC5
TOC4
RESERV
ffl5
ffl4
ED
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
PN7462 family HW user manual
Bit 3
Bit 2
Bit 1
pres pup
CLKAUX
IOAUXen
en
en
PD3
PD2
PD1
PD11
PD10
PD9
ftc3
ftc2
ftc1
GT3
GT2
GT1
PROT
T/R
LCT
dispe
disft
MAN BGT AUTO
SAN
ACC2
ACC1
vccsel1
vccsel0
WARM
EC3
EC2
EC1
MCL3
MCL2
MCL1
MCL11
MCL10
MCL9
MCH3
MCH2
MCH1
MCH11
MCH10
MCH9
clk_sr1
clk_sr0
io_sr1
UR3
UR2
UR1
UT3
UT2
UT1
TOL3
TOL2
TOL1
TOL11
TOL10
TOL9
TOL19
TOL18
TOL17
TOC3
TOC2
TOC1
ffl3
ffl2
ffl1
UM10858
Bit 0
Reset
value
softreset
XXXX
0001
PD0
0111
0100
PD8
0000
0001
ftc0
0000
0001
GT0
0000
0000
CONV
XX00
0000
0000
CONV
0000
XX00
ACC0
0000
START
11X0
0000
EC0
1010
1010
MCL0
0111
0100
MCL8
1010
0100
MCH0
0111
0100
MCH8
1010
0100
io_sr0
XX00
0000
UR0
0000
0000
0000
Ut0
0000
TOL0
0000
0000
TOL8
0000
0000
0000
TOL16
0000
TOC0
0000
0000
ffl0
XX00
0000
© NXP B.V. 2018. All rights reserved.
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