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General register ER7 has the function of stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2.5 shows the
stack.
SP (ER7)
Figure 2.5 Relationship between Stack Pointer and Stack Area
2.3.2
Program Counter (PC)
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length
of all CPU instructions is 2 bytes (one word) or a multiple of 2 bytes, so the least significant PC
bit is ignored. When an instruction is fetched, the least significant PC bit is regarded as 0. The PC
is initialized when the start address is loaded by the vector address generated during reset
exception-handling sequence.
2.3.3
Condition Code Register (CCR)
This 8-bit register contains internal CPU status information, including the interrupt mask bit (I)
and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. The I bit is initialized
to 1 by reset exception-handling sequence, but other bits are not initialized.
Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. NMI is accepted
regardless of the I bit setting.
Bit 6—User Bit (UI): Can be written and read by software using the LDC, STC, ANDC, ORC,
and XORC instructions.
Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B
instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0
otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is
set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L,
SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or
borrow at bit 27, and cleared to 0 otherwise.
Free area
Stack area
17
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