Exit From Sleep Mode; Software Standby Mode; Transition To Software Standby Mode; Exit From Software Standby Mode - Hitachi H8/3035 Series Hardware Manual

16.3.2 Exit from Sleep Mode

Sleep mode is exited by an interrupt, or by input at the
Exit by Interrupt: An interrupt terminates sleep mode and causes a transition to the interrupt
exception handling state. Sleep mode is not exited by an interrupt source in an on-chip
supporting module if the interrupt is disabled in the on-chip supporting module. Sleep mode is
not exited by an NMI interrupt if masked in the CPU.
5(6
5(6
Exit by Input: Low input at the
67%< 67%<
Exit by Input: Low input at the
mode.

16.4 Software Standby Mode

16.4.1 Transition to Software Standby Mode

To enter software standby mode, execute the SLEEP instruction while the SSBY bit is set to 1 in
SYSCR.
In software standby mode, current dissipation is reduced to an extremely low level because the
CPU, clock, and on-chip supporting modules all halt. The on-chip supporting modules are reset.
As long as the specified voltage is supplied, however, CPU register contents and on-chip RAM
data are retained. The settings of the I/O ports are also held.

16.4.2 Exit from Software Standby Mode

Software standby mode can be exited by input of an external interrupt at the NMI, IRQ
or IRQ pin, or by input at the
2
Exit by Interrupt: When an NMI, IRQ
clock oscillator begins operating. After the oscillator settling time selected by bits STS2 to STS0
in SYSCR, stable clock signals are supplied to the entire chip, software standby mode ends, and
interrupt exception handling begins. Software standby mode is not exited if the interrupt enable
bits of interrupts IRQ , IRQ
0
CPU.
5(6
5(6
Exit by Input: When the
are supplied immediately to the entire chip. The
the clock oscillator to stabilize. When
67%< 67%<
Exit by Input: Low input at the
386
5(6
pin exits from sleep mode to the reset state.
67%<
pin exits from sleep mode to hardware standby
5(6 67%<
or pin.
, IRQ , or IRQ
0 1
, and IRQ are cleared to 0, or if these interrupts are masked in the
1 2
5(6
input goes low, the clock oscillator starts and clock pulses
5(6
5(6
goes high, the CPU starts reset exception handling.
67%<
pin causes a transition to hardware standby mode.
5(6 67%<
or pin.
interrupt request signal is received, the
2
signal must be held low long enough for
, IRQ ,
0 1