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6.5.2
Clearing the Standby Mode
The standby mode is cleared by an interrupt or by input at the RES pin.
• Clearing by interrupt
When an interrupt is requested, the system clock pulse generator starts. After the time set in
bits STS2–STS0 in SYSCR1 has elapsed, a stable system clock signal is supplied to the entire
chip, the standby mode is cleared, and interrupt exception handling starts. The standby mode is
not cleared if the I bit of CCR is set to 1 or the requested interrupt is disabled in the interrupt
enable register.
• Clearing by RES input
When the RES pin goes low, the system clock pulse generator starts. After the pulse generator
output has stabilized, the CPU starts reset exception handling if the RES pin is driven high.
Since system clock signals are supplied to the entire chip as soon as the system clock pulse
generator starts functioning, the RES pin must be kept low until the pulse generator output
stabilizes.
6.5.3
Oscillator Settling Time after the Standby Mode is Cleared
• When a crystal oscillator is used
Table 6.5 lists the settings for various operating frequencies. Bits STS2 to STS0 in SYSCR1
must be set so that the waiting time is longer than the oscillator settling time.
Table 6.5
Operating Frequency and Waiting Time (ø = øosc)
STS2
STS1
STS0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
• When an external clock is used
Any values can be set. Normally the minimum time (STS2 = STS1 = STS0 = 1) should be set.
Waiting Time
10 MHz 8 MHz
8,192 states
0.8
16,384 states
1.6
32,768 states
3.3
65,536 states
6.6
131,072 states
13.1
1,024 states
0.10
128 states
0.01
16 states
0.00
4 MHz
2 MHz
1.6
2.0
4.1
2.0
4.1
8.2
4.1
8.2
16.4
8.2
16.4
32.8
16.4
32.8
65.5
0.13
0.26
0.51
0.02
0.03
0.06
0.00
0.00
0.01
1 MHz
0.5 MHz
8.1
16.4
16.4
32.8
32.8
65.5
65.5
131.1
131.1
262.1
1.02
2.05
0.13
0.26
0.02
0.03
(Unit: ms)
91
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