Duty Adjustment Circuit; Prescalers; Frequency Divider; Register Configuration - Hitachi H8/3048 Hardware Manual

Single-chip microcomputer

Table of Contents

19.3 Duty Adjustment Circuit

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When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty

cycle of the clock signal from the oscillator to generate the signal that becomes the system clock.

The prescalers divide the system clock (ø) to generate internal clocks (ø/2 to ø/4096).

The frequency divider divides the duty-adjusted clock signal to generate the system clock (ø). The

frequency division ratio can be changed dynamically by modifying the value in DIVCR, as

described below. Power consumption in the chip is reduced in almost direct proportion to the

frequency division ratio. The system clock generated by the frequency divider can be output at the

Table 19-4 summarizes the frequency division register.

Table 19-4 Frequency Division Register

Division control register

Note: * The lower 16 bits of the address are shown.

DIVCR is an 8-bit readable/writable register that selects the division ratio of the frequency

Initial value

DIVCR is initialized to H'FC by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Reserved bits

Abbreviation

Initial Value

Divide bits 1 and 0

These bits select the

frequency division ratio