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Figure 7.11 shows the flash memory state transition diagram.
Program mode
Erase mode
RD VF PR ER FLER = 0
Error
occurrence
Error protection mode
RD VF PR ER FLER = 1
Notation
RD: Memory read possible
VF: Verify-read possible
PR: Programming possible
ER: Erasing possible
7.8
Interrupt Handling when Programming/Erasing Flash Memory
All interrupts, including NMI interrupt is disabled when flash memory is being programmed or
erased (when the P or E bit is set in FLMCR1), and while the boot program is executing. There are
three reasons for this:
(1) Interrupt during programming or erasing might cause a violation of the programming or
erasing algorithm, with the result that normal operation could not be assured.
(2) In the interrupt exception handling sequence during programming or erasing, the vector would
not be fetched correctly, possibly resulting in MCU runaway.
(3) If interrupt occurred during boot program execution, it would not be possible to execute the
normal boot mode sequence.
Notes: 1. Interrupt requests must be disabled inside and outside the MCU until the programming
control program has completed programming.
RES = 0
Error occurrence
(software standby)
Software
standby mode
Software standby
mode release
RD: Memory read not possible
VF: Verify-read not possible
PR: Programming not possible
ER: Erasing not possible
Figure 7.11 Flash Memory State Transitions
(hardware protection)
RD VF PR ER FLER = 0
RES = 0
RES = 0
Error protection mode
(standby)
RD VF PR ER FLER = 1
FLMCR1, FLMCR2, (except bit FLER)
EBR1, initialization state
Reset
FLMCR1, FLMCR2,
EBR1, initialization
state
121
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