4.2 Transfer Cycle
CPU-0
CPU-1
CPU-2
Memory transfer explained in Section 4.1 is performed according to the timing chart shown in
Figure 4-3. Each horizontal reference line above is a time axis.
Sharing starts when CPU-0 transfers area A and ends when CPU-2 transfers area C. Memory
transfer areas are shared by periodically repeating this cycle.
The transfer cycle depends on the module No. switches, the number of modules installed, and the
amount of data transferred. This cycle is calculated from the expressions shown in Table 4-1.
Table 4-1 Expressions for Calculating Transfer Cycle
Module No. SW
W: Total ring length (km)
X: Number of operating modules
Y: Amount of word data (words)
Z: Amount of bit data (points)
A
B
C
Figure 4-3 Transfer Cycle
Expressions for Calculating Transfer Cycle
0, 1
192 - 0.5964X + 0.0146Y + 0.0009Z + 0.005WX (ms)
2, 3
96 - 0.5964X + 0.0146Y + 0.0009Z + 0.005WX (ms)
4, 5
48 - 0.5964X + 0.0146Y + 0.0009Z + 0.005WX (ms)
6, 7
24 - 0.5964X + 0.0146Y + 0.0009Z + 0.005WX (ms)
A
B
Transfer cycle
4-3
4 USER GUIDE
C