Appendix E Timing Of Transition To And Recovery From Hardware Standby Mode - Hitachi H8/3035 Series Hardware Manual

Appendix E Timing of Transition to and Recovery from
Timing of Transition to Hardware Standby Mode
(1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the
system clock cycles before the
67%<
low until goes low (minimum delay from
STBY
RES
(2) To retain RAM contents with the RAME bit cleared to 0 in SYSCR,
driven low as in (1).
Timing of Recovery from Hardware Standby Mode: Drive the
approximately 100 ns before
STBY
RES
Hardware Standby Mode
67%<
signal goes low, as shown below.
67%<
≥ 10t
t
1 cyc
67%<
goes high.
t ≥ 100 ns
5(6
5(6
5(6
low to high: 0 ns).
≥ 0 ns
t
2
5(6
does not have to be
5(6
signal low
t
OSC
signal low 10
must remain
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