Access To External Address Space; Figure 2.17 Access Cycle For On-Chip Supporting Modules; Figure 2.18 Pin States During Access To On-Chip Supporting Modules - Hitachi H8/3062 Hardware Manual

φ
Address bus
Internal read signal
Read
access
Internal data bus
Internal write signal
Write
access
Internal data bus

Figure 2.17 Access Cycle for On-Chip Supporting Modules

φ
Address bus
AS RD HWR LWR
, , ,
D to D
15 0

Figure 2.18 Pin States during Access to On-Chip Supporting Modules

2.9.4

Access to External Address Space

The external address space is divided into eight areas (areas 0 to 7). Bus-controller settings
determine whether each area is accessed via an 8-bit or 16-bit data bus, and whether it is accessed
in two or three states. For details see section 6, Bus Controller.
T state
1
T
1
High
High impedance
Bus cycle
T state
2
Address
Read data
Write data
T
2
Address
T state
3
T
3
65