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CHAPTER 15 8/16-BIT PPG TIMER
15.3.3 PPG0 to PPG5 Output Control Registers
(PPG01, PPG23, PPG45)
This section describes the configuration and functions of the PPG0 to PPG5 output
control registers (PPG01, PPG23, PPG45).
■
PPG0 to PPG5 output control registers (PPG01, PPG23, PPG45)
The bit configuration of the PPG0 to 5 output control registers (PPG01, PPG23, PPG45) is
described below.
ch.0,ch.1 000040
ch.2,ch.3 000042
ch.4,ch.5 000044
The functions of the bits in the PPG0 to PPG5 output control registers (PPG01, PPG23, PPG45)
are described below.
[bit7, bit6, bit5] PCS2 to 0:ppg Count Select (count clock selection)
These bits are used to select the operation clock for the down counter of channels 1, 3, and
5.
PCS2
0
0
0
0
1
1
•
These bits are initialized to "000
•
Reading and writing are allowed.
Note:
In 8-bit prescaler + 8-bit PPG mode and in 16-bit PPG mode, setting bits PCS2 to 0 is disabled
since the PPG of channels 1,3, and 5 receives the counter clock signal from channels 0,2, and 4.
328
7
6
5
H
PCS2 PCS1 PCS0 PCM2 PCM1 PCM0
H
H
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Read/write
(0)
(0)
(0)
(0)
PCS1
PCS0
0
0
0
1
1
0
1
1
0
0
1
1
4
3
2
1
Reserved Reserved
(0)
(0)
(0)
Operation mode
Peripheral clock (62.5 ns machine clock for 16 MHz)
Peripheral clock/2 (125 ns machine clock for 16 MHz)
Peripheral clock/4 (250 ns machine clock for 16 MHz)
Peripheral clock/8 (500 ns machine clock for 16 MHz)
Peripheral clock/16 (1 μs machine clock for 16 MHz)
Input clock from the timebase counter
9
x 250 ns = 128 μs oscillation for 4 MHz)
(2
" at reset.
B
0
PPG01, PPG23, PPG45
Output control register
(0)
Initial value
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