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5.3.1
Timebase timer control register (TBTC)
The timebase timer control register (TBTC) provides the following settings:
• Selecting the interval time of the timebase timer
• Clearing the count value of the timebase timer
• Enabling or disabling the interrupt request when an overflow occurs
• Checking and clearing the state of the interrupt request flag when an overflow occurs
I Timebase timer control register (TBTC)
15
14
13
R/W
-
-
R/W : Read/write
W
: Write only
X
: Undefined
: Reset value
-
: Unused
Figure 5.3-2 Timebase timer control register (TBTC)
8
12
11
10
9
R/W R/W W R/W R/W
bit9
TBC1
HCLK: Oscillation clock
The parenthesized values are provided when the oscillation clock
operates at 4 MHz.
bit10
TBR
bit11
TBOF
bit12
TBIE
bit15
Reserved
Reset value
1 X X 0 0 1 0 0
B
bit8
TBC0
Interval time select bit
12
0
0
2
/HCLK (approx. 1.0ms)
14
0
1
2
/HCLK (approx. 4.1ms)
16
1
0
2
/HCLK (approx. 16.4ms)
19
1
1
2
/HCLK (approx. 131.1ms)
Timebase timer counter clear bit
Read
0
-
1
1 is always read.
Over flow interrupt request flag bit
Read
0
Without over flow of
selected count bit
1
With over flow of
selected count bit
Over flow interrupt enable bit
0
Disabling of over flow interrupt request
1
Enabling of over flow interrupt request
Reserved bit
1
1 is always set.
CHAPTER 5 Timebase timer
Write
Clear timebase timer counter.
Clear TBOF bit.
No effect.
Write
Being clear.
No effect
197
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