Timebase Timer Control Register (Tbtc); Figure 5.3-1 Timebase Timer Control Register (Tbtc); Table 5.3-1 Timebase Timer Control Register (Tbtc) Bits - Fujitsu F2MC-8L Series Hardware Manual

CHAPTER 5 TIMEBASE TIMER
5.3

Timebase Timer Control Register (TBTC)

The timebase timer control register (TBTC) is used to select the interval timer bit, clear
the counter, control interrupts, and check the state of the timebase timer.
Timebase Timer Control Register (TBTC)
Address Bit 7
000A TBOF
H
R/W
R/W : Readable and writable
W : Write-only
— : Unused
X : Indeterminate
: Initial value

Table 5.3-1 Timebase Timer Control Register (TBTC) Bits

Bit
TBOF:
Bit 7 Overflow interrupt request
flag bit
136

Figure 5.3-1 Timebase Timer Control Register (TBTC)

Bit 6 Bit 5 Bit 4 Bit 3
TBIE — — —
R/W
Bit 2 Bit 1 Bit 0
TBC1 TBC0 TBR
R/W R/W W
Timebase timer initialization bit
TBR
Read
0 —
Reading always returns
1
"1".
TBC1 TBC0
0 0
0 1
1 0
1 1
F : Main clock source oscillation
CH
TBIE Interrupt request enable bit
0 Disables interrupt request output.
1 Enables interrupt request output.
Overflow interrupt request flag bit
TBOF
Read
No overflow on specified
0
bit
1 Overflow on specified bit
• This bit is set to "1" when an overflow occurs on the
specified bit of the timebase timer counter.
• An interrupt request is output when both this bit and the
interrupt request enable bit (TBIE) are "1".
• Writing "0" clears this bit. Writing "1" has no effect and
does not change the bit value.
Initial value
00XXX000
B
Write
Clears the timebase timer
counter.
No effect. The bit does not
change.
Interval time select bits
2 13 /F
CH
2 15 /F
CH
18
2 /F
CH
2 22 /F
CH
Write
Clears this bit.
No effect. The bit does not
change.
Function