Timebase Timer Control Register (Tbtc) - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 9 TIMEBASE TIMER
9.3

Timebase Timer Control Register (TBTC)

This register selects the interval time, clears the counter, controls interrupt requests,
and checks the state.
I Timebase timer control register (TBTC)
0000A9
H
R/W : Read and write enabled
W : Write only
- : Not used
x : Undefined
HCLK : Oscillation clock
: Initial value
194
Figure 9.3-1 Timebase timer control register (TBTC)
bit15 bit14 bit13 bit12 bit11
RESV TBIE TBOF TBR TBC1 TBC0
R/W R/W R/W
bit10 bit9 bit8 bit7
(TBTC)
W R/W R/W
Interval time selection bit
TBC1 TBC0
12
0 0 2 /HCLK (approximately 1.0 ms)
0 1 14
2 /HCLK (approximately 4.1 ms)
16
1 0 2 /HCLK (approximately 16.4 ms)
19
1 1 2 /HCLK (approximately 131 ms)
The value during operation of the oscillation clock at 4 MHz
is shown in ( ).
Timebase timer initializing bit
TBR
During reading
Clears TBOF bit of timebase
0
timer counter
"1" is always read No change, no effect on
1
and output other functions
Interrupt request flag bit
TBOF
During reading
No overflow of
0
Clears this bit.
specified bit
Overflow of specified No change, no effect on
1
bit other functions
Interrupt request permit bit
TBIE
0 Prohibits interrupt request output
1 Permits interrupt request output
RESV Reserved bit
Always write "1" to this bit
Initial value
bit0
1XX00100
B
During writing
During writing