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CHAPTER 3 CPU
3.8.3
Low-power consumption mode control register (LPMCR)
The low-power consumption mode control register (LPMCR) transits an operation mode
to, and cancels the low-power consumption modes, generates an internal reset signal,
and sets the halt cycle count in the CPU intermittent operation mode.
I Low-power consumption mode control register (LPMCR)
Figure 3.8-4 Low-power consumption mode control register (LPMCR)
7
6
5
W
W
R/W
R/W
: Read/Write
W
: Write only
: Reset value
130
4
3
2
1
0
W
W
R/W
R/W
R/W
bit0
Reserved
0
bit2
CG1 CG0
0
0
1
1
bit3
TMD
0
1
bit4
RST
0
1
bit5
SPL
0
1
bit6
SLP
0
1
bit7
STP
0
1
Reset value
00011000
B
Reserved bit
Be sure to set this bit to 0.
bit1
CPU suspendedcycle number select bit
0
0 cycle (CPU clock = peripheral clock)
1
8 cycle (CPU clock: peripheral clock = 1: approx.3 to 4)
0
16 cycle (CPU clock: peripheral clock = 1: approx.5 to 6)
1
32 cycle (CPU clock: peripheral clock = 1: approx.9 to 10)
Clock mode bit
Transfer to clock mode or timebase timer mode
No effect
Internal reset signal generation bit
Generate the internal reset of 3-machine cycle
No effect
Pin state specification bit
Hold I/O pin state
High-Z
Only in timebase timer, clock and stop mode
Sleep mode bit
No effect
Change to sleep mode
Stop mode bit
No effect
Change to stop mode
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